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cy8c28243, cy8c 28403, cy8c28413 cy8c28433, cy8c 28445, cy8c28452 cy8c28513, cy8c 28533, cy8c28545 cy8c28623, cy8c 28643, cy8c28645 psoc ? programmable system-on-chip? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-48111 rev. *l revised may 8, 2013 psoc ? programmable system-on-chip? features varied resource options within one psoc ? device group powerful harvard-architecture processor ? m8c processor speeds up to 24 mhz ? 8 8 multiply, 32-bit accumulate ? low power at high speed ? operating voltage: 3.0 v to 5.25 v ? operating voltages down to 1.5 v using on-chip switched mode pump (smp) ? industrial temperature range: ?40 c to +85 c advanced reconfigurable peripherals (psoc blocks) ? up to 12 rail-to-rail analog psoc blocks provide: ? up to 14-bit adcs ? up to 9-bit dacs ? programmable gain amplifiers ? programmable filters and comparators ? multiple adc configurations ? dedicated sar adc, up to 142 ksps with sample and hold ? up to 4 synchronized or independent delta-sigma adcs for advanced applications ? up to 4 limited type e analog blocks provide: ? dual channel capacitive sensing capability ? comparators with programmable dac reference ? up to 10-bit single-slope adcs ? up to 12 digital psoc blocks provide: ? 8- to 32-bit timers and count ers, 8- and 16-bit pulse-width modulators (pwms) ? shift register, crc, and prs modules ? up to 3 full-duplex uarts ? up to 6 half-duplex uarts ? multiple variable data length spi ? masters or slaves ? connectable to all gpios ? complex peripherals by combining blocks precision, programmable clocking ? internal 2.5% 24/48 mhz main oscillator ? optional 32.768 khz crystal for precise on-chip clocks ? optional external oscillator, up to 24 mhz ? internal low speed, low power oscillator for watchdog and sleep functionality flexible on-chip memory ? 16 kb flash program storage 50,000 erase/write cycles ? 1-kb sram data storage ? in-system serial programming (issp ? ) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25 ma sink, 10 ma drive on all gpios ? pull-up, pull-down, high z, stro ng, or open-drain drive modes on all gpios ? analog input on all gpios ? 30 ma analog outputs on gpios ? configurable interrupt on all gpios additional system resources ? up to two hardware i 2 c resources ? each resource implements slav e, master, or multi-master modes ? operation between 0 and 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? flexible internal voltage references ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc designer?) ? full featured in-circuit emulator, and programmer ? full speed emulation ? flexible and functional breakpoint structure ? 128 kb trace memory digital system sram 1k interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16k digital block array 2 macs switch mode pump internal voltage ref. digital clocks por and lvd system resets 4 type 2 decimators system resources analog system analog ref. analog input muxing 2 i 2 c blocks port 4 port 3 port 2 port 1 port 0 analog drivers system bus analog block array port 5 logic block diagram
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 2 of 80 contents psoc functional overview .............................................. 3 the psoc core ........................................................... 3 the digital system ...................................................... 3 the analog system ..................................................... 4 system resources ...................................................... 7 psoc device characteristics . ..................................... 7 getting started .................................................................. 8 application notes ........................................................ 8 development kits ........................................................ 8 training ....................................................................... 8 cypros consultants .................................................... 8 solutions library .......................................................... 8 technical support ....................................................... 8 development tools .......................................................... 9 psoc designer software subsyst ems .......... .............. 9 designing with psoc designer ..................................... 10 select user modules ................................................. 10 configure user modules ............................................ 10 organize and connect .............. .............. ........... ....... 10 generate, verify, and debug ..................................... 10 pinouts ............................................................................ 11 20-pin part pinout .................................................... 11 28-pin part pinout ..................................................... 12 44-pin part pinout .................................................... 13 48-pin part pinout ..................................................... 14 56-pin part pinout ..................................................... 15 register reference ......................................................... 17 register conventions ................................................ 17 register mapping tables .......................................... 17 electrical specifications ................................................ 32 absolute maximum ratings .... ................................... 33 operating temperature ............................................. 33 dc electrical characteristics ..................................... 34 ac electrical characteristics ..................................... 52 packaging information ................................................... 62 packaging dimensions .............................................. 62 thermal impedances ................................................ 66 capacitance on crystal pins .............. .............. ........ 66 solder reflow specifications ..................................... 66 development tool selection .. .............. .............. ........... 67 software .................................................................... 67 development kits ...................................................... 67 evaluation tools ........................................................ 67 device programmers ............. .................................... 68 accessories (emulation and programming) .............. 68 ordering information ...................................................... 69 ordering code definitions ..... .................................... 70 acronyms ........................................................................ 71 acronyms used ......................................................... 71 reference documents .................................................... 71 document conventions ................................................. 72 units of measure ....................................................... 72 numeric conventions ............ .................................... 72 glossary .......................................................................... 72 silicon errata for cy8c28243, cy8c28403, cy8c28413, cy8c28433, cy8c28445, cy8c28452, cy8c28513, CY8C28533, cy8c28545, cy8c28623, cy8c28643, cy8c2 8645 ............. .............. 77 part numbers affected .............................................. 77 qualification status ................................................... 77 errata summary .................... .................................... 77 document history page ................................................. 79 sales, solutions, and legal information ...................... 80 worldwide sales and design s upport ......... .............. 80 products .................................................................... 80 psoc solutions ......................................................... 80
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 3 of 80 psoc functional overview the psoc family consists of many devices with on-chip controllers. these devices are designed to replace multiple traditional mcu based system components with one low cost single chip programmable component. a psoc device includes configurable analog bl ocks, digital blocks, and interco nnections. this architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. in addition, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts and packages. the cy8c28xxx group of psoc devices described in this datasheet have multiple re source configuration options available. therefore, not ever y resource mentioned in this datasheet is available for each cy8c28xxx subgroup. the cy8c28x45 subgroup has a full feature set of all resources described. there are six more s egmented subgroups that allow designers to use a device with only the resources and function- ality necessary for a specific application. see ta b l e 2 on page 8 to determine the resources available for each cy8c28xxx subgroup. the same information is also presented in more detail in the ordering information section. the architecture for this specific psoc device family, as shown in the logic block diagram on page 1, consists of four main areas: psoc core, digital system, analog system, and system resources. the configurable gl obal bus system allows all the device resources to be combined into a complete custom system. psoc cy8c28xxx family devices have up to six i/o ports that connect to the global digital and analog interconnects, providing access to up to 12 di gital blocks and up to 16 analog blocks. the psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable general purpose i/o (gpio). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8-bit harvard architecture microcontroller. memory encompasses 16k bytes of flash for program storage, 1k bytes of sram for data storage. the psoc device incorpo- rates flexible internal clock generators, including a 24 mhz internal main oscillator (imo) ac curate to 2.5% over temperature and voltage. a low power 32 khz internal low speed oscillator (ilo) is provided for the sleep timer and watch dog timer (wdt). the 32.768 khz external crystal oscillator (eco) is available for use as a real time clock (rtc) and can optionally generate a crystal-accurate 24 mhz sy stem clock using a pll. psoc gpios provide connections to the cpu, and digital and analog resources. each pin?s drive mode may be selected from 8 options, which allows great flex ibility in external interfacing. every pin also has the capabili ty to generate a system interrupt on high level, low level, and change from last read. the digital system the digital system is composed of up to 12 configurable digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to create 8, 16, 24, and 32-bit peripherals, which are ca lled user modules. the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. figure 1. digital system block diagram [1] digital peripheral configurations include: pwms (8- and 16-bit, one-shot and multi-shot capability) pwms with dead band/kill (8- and 16-bit) counters (8 to 32 bit) timers (8 to 32 bit) full-duplex 8-bit uarts (up to 3) with selectable parity half-duplex 8-bit uarts (up to 6) with selectable parity variable length spi slave and master ? up to 6 total slaves and masters (8-bit) ? supports 8 to 16 bit operation i 2 c slave, master, or multi-master (up to 2 available as system resources) irda (up to 3) pseudo random sequence generators (8 to 32 bit) cyclical redundancy checker/generator (16 bit) shift register (2 to 32 bit) digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 8 8 8 gie[7:0] gio[7:0] global digital interconnect port 4 port 3 port 2 port 1 port 0 port 5 goo[7:0] goe[7:0] row input configuration row 0 dbc00 dbc01 dcc02 dcc03 4 4 row output configuration row 1 dbc10 dbc11 dcc12 dcc13 row input configuration 4 4 row output configuration row 2 dbc20 dbc21 dcc22 dcc23 row input configuration 4 4 row output configuration note 1. cy8c28x52 devices do not have digital block row 2. they have two digital rows with eight total digital blocks.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 4 of 80 the analog system the analog system is composed of up to 16 configurable analog blocks, each containing an opamp ci rcuit that allows the creation of complex analog signal flows. some devices in this psoc family have an analog multiplex bus that can connect to every gpio pin. this bus can also connect to the analog system for analysis with comparators and analog-to-digital converters. it can be split into two sections for simultaneous dual-channel processing. some of the more common psoc analog functions (most available as user modules) are: analog-to-digital converters (6 to 14-bit resolution, up to 4, selectable as incremental or delta sigma) dedicated 10-bit sar adc with sample rates up to 142 ksps synchronized, simultaneous delta sigma adcs (up to 4) filters (2 to 8 pole band-pass, low pass, and notch) amplifiers (up to 4, with selectable gain to 48x) instrumentation amplifiers (up to 2, with selectable gain to 93x) comparators (up to 6, with 16 selectable thresholds) dacs (up to 4, with 6 to 9-bit resolution) multiplying dacs (up to 4, with 6 to 9-bit resolution) high current output drivers (up to 4 with 30 ma drive) 1.3 v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible figure 2. analog system block diagram for cy8c28x45 and cy8c28x52 devices acc00 acc01 block array array input configuration aci1[1:0] aci2[1:0] acc02 acc03 asc12 asd13 asd22 asc23 asd20 aci0[1:0] aci3[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference ace00 ace01 ase10 ase11 analog mux bus all gpio aci4[1:0] aci5[1:0]
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 5 of 80 figure 3. analog system block diagram for cy8c28x43 devices figure 4. analog system block diagram for cy8c28x33 devices acc00 acc01 block array array input configuration aci1[1:0] aci2[1:0] acc02 acc03 asc12 asd13 asd22 asc23 asd20 aci0[1:0] aci3[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference analog mux bus all gpio acc00 acc01 block array array input configuration aci1[1:0] asd20 aci0[1:0] p0[6] p0[4] p0[2] p0[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference ace00 ace01 ase10 ase11 aci4[1:0] aci5[1:0] analog mux bus all gpio
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 6 of 80 figure 5. analog system block diagram for cy8c28x23 devices figure 6. analog system block diagram for cy8c28x13 devices acc00 acc01 block array array input configuration aci1[1:0] asd20 aci0[1:0] p0[6] p0[4] p0[2] p0[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference block array array input configuration aci1[1:0] aci0[1:0] p0[6] p0[4] p0[2] p0[0] p0[7] p0[5] p0[3] p0[1] reference generators agndin refin bandgap refhi reflo agnd interface to digital system m8c interface (address bus, data bus, etc.) analog reference ace00 ace01 ase10 ase11 analog mux bus all gpio
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 7 of 80 system resources system resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. additional resources in clude a multiplier, multiple decimators, switch mode pump, low voltage detection, and power on reset. statements descri bing the merits of each system resource follow: digital clock dividers provide three customizable clock frequencies for use in applications. th e clocks can be routed to both the digital and analog systems. additional clocks can be generated using di gital psoc blocks as clock dividers. multiply accumulate (mac) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. up to four decimators provide custom hardware filters for digital signal processing applications such as delta-sigma adcs and capsense capacitive sensor measurement. up to two i 2 c resources provide 0 to 400 khz communication over two wires. slave, master, and multi-master modes are all supported. i 2 c resources have hardware address detection capability. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3 v reference provides an absolute reference for the analog system, including adcs and dacs. an integrated switch mode pump (smp) generates normal operating voltages from a single 1.5 v battery cell, providing a low cost boost converter. psoc device characteristics depending on your psoc device characteristic s, the digital and ana log systems can have 16, 8, or 4 digital blocks, and 12, 6, o r 4 analog blocks. table 1 on page 7 lists the resources available for specific psoc device groups. the psoc device covered by this datasheet is highlighted in this table. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 up to 64 4 16 up to 12 4 4 12 2 k 32 k cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12 + 4 [2] 1 k 16 k cy8c27x43 up to 44 2 8 up to 12 4 4 12 256 16 k cy8c24x94 up to 56 1 4 up to 48 2 2 6 1 k 16 k cy8c24x23a up to 24 1 4 up to 12 2 2 6 256 4 k cy8c23x33 up to 26 1 4 up to 12 2 2 4 256 8 k cy8c22x45 up to 38 2 8 up to 38 0 4 6 [2] 1 k 16 k cy8c21x45 up to 24 1 4 up to 24 0 4 6 [2] 512 8 k cy8c21x34 up to 28 1 4 up to 28 0 2 4 [2] 512 8 k cy8c21x23 up to 16 1 4 up to 8 0 2 4 [2] 256 4 k cy8c20x34 up to 28 0 0 up to 28 0 0 3 [2,3] 512 8 k cy8c20xx6 up to 36 0 0 up to 36 0 0 3 [2,3] up to 2 k up to 32 k notes 2. limited analog functionality. 3. two analog blocks and one capsense ? .
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 8 of 80 the devices covered by this datasheet all have the same architec ture, specifications, and ratings. however, the amount of some hardware resources varies from device to device within the group . the following table lists resources available for the specifi c device subgroups covered by this datasheet. getting started for in depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics an d skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. table 2. cy8c28xxx device characteristics psoc part number capsense digital blocks regular analog blocks limited analog blocks hw i 2 c decima- tors digital i/o analog inputs analog outputs cy8c28x03n120020up to 24up to 8 0 cy8c28x13y120412up to 40up to 40 0 cy8c28x23n126022up to 44up to 10 2 cy8c28x33 y126414up to 40up to 40 2 cy8c28x43 n 12 12 0 2 4 up to 44 up to 44 4 cy8c28x45 y 12 12 4 2 4 up to 44 up to 44 4 cy8c28x52 y 8 12 4 1 4 up to 24 up to 24 4 notes 4. has 12 regular analog blocks and fo ur limited type-e analog blocks. 5. limited analog functionality . 6. two analog blocks and one capsense.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 9 of 80 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application require ments. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, incl uding in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/transmitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (d acs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this lets you to use more than 100 percent of psoc's resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also lets you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-s ensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a ba se unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 10 of 80 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed-function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and lowering inventory costs. these configurable resources, called ps oc blocks, have the ability to implement a wide variety of user-selectable functions. the psoc development process is: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the select ed function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pwm user module configures one or more digital psoc blocks, one for each eight bits of resolution. using these parameters, you can establish the pulse width and duty cycle. configure the parameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. all of the user modules are documented in datasheets that may be viewed di rectly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the us er module and provide performance specifications. each datasheet de scribes the use of each user module parameter, and other information that you may need to successfully implement your design. organize and connect build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate configuration files? step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides apis with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. a complete code development environment lets you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer's debugger (accessed by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full-speed. psoc designer debugging capabilities rival those of syst ems costing many times more. in addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. it lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 11 of 80 pinouts this section describes, lists, and illustrates the cy8c28xxx psoc device pins and pinout configurations. the cy8c28xxx psoc devices are available in a variety of packages which are listed and illustrated in the following tables. eve ry port pin (labeled with a ?p?) is capable of digital i/o. however, v ss , v dd , smp, and xres are not capable of digital i/o. 20-pin part pinout table 3. 20-pin part pinout (ssop) pin no. type pin name description cy8c28243 20-pin psoc device digital analog 1 i/o i, m, s p0[7] analog column mux and sar adc input. [8] 2 i/o i/o, m, s p0[5] analog column mux and sar adc input. analog column output. [8, 9] 3 i/o i/o, m, s p0[3] analog column mux and sar adc input. analog column output. [8, 9] 4 i/o i, m, s p0[1] analog column mux and sar adc input. [8] 5 output smp switch mode pump (smp) connection to external components. 6 i/o m p1[7] i2c0 serial clock (scl). 7 i/o m p1[5] i2c0 serial data (sda). 8 i/o m p1[3] 9 i/o m p1[1] crystal input (xtalin), i2c0 serial clock (scl), issp-sclk [7] . 10 power v ss ground connection. 11 i/o m p1[0] crystal output (xtalout), i2c0 serial data (sda), issp-sdata [7] . 12 i/o m p1[2] i2c1 serial data (sda). [10] 13 i/o m p1[4] optional external clock input (extclk). 14 i/o m p1[6] i2c1 serial clock (scl). [10] 15 input xres active high exter nal reset with internal pull-down. 16 i/o i, m, s p0[0] analog column mux and sar adc input. [8] 17 i/o i/o, m, s p0[2] analog column mux and sar adc input. analog column output. [8, 11] 18 i/o i/o, m, s p0[4] analog column mux and sar adc input. analog column output. [8, 11] 19 i/o i, m, s p0[6] analog column mux and sar adc input. [8] 20 power v dd supply voltage. legend : a = analog, i = input, o = output, s = sar adc input, and m = analog mux bus input. ssop 2 1 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vdd p0[6], m, ai, s p0[4], m, aio, s p0[2], m, aio, s p0[0], m, ai, s xres p1[6], m, i2c1 scl p1[4], m, extclk p1[2], m, i2c1 sda p1[0], m, xtalout, i2c0 sda s, ai, m, p0[7] s, aio, m, p0[5] s, aio, m, p0[3] s, ai, m, p0[1] smp i2c0 scl, m, p1[7] i2c0 sda, m, p1[5] m, p1[3] i2c0 scl, xtalin, m, p1[1] vss notes 7. these are the issp pins, which are not high z at por (power on reset). see the psoc technical reference manual for cy8c28xxx psoc devices for details. 8. cy8c28x52 and cy8c28x23 devices do not have a sar adc. therefore, this pin does not function as a sar adc input for these dev ices. 9. cy8c28x13 and cy8c28x03 devices do not have any analog output buffers. therefore, this pin does not functi on as an analog col umn output for these devices. 10. cy8c28x52, cy8c28x13, and cy8c28x3 3 devices only have one i2c block. therefore, this gpio does not function as an i2c pin fo r these devices. 11. cy8c28x33, cy8c28x23, cy8c28x13, and cy8c 28x03 devices do not have an analog output buf fer for this pin. therefore, this pin does not function as an analog column output for these devices.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 12 of 80 28-pin part pinout table 4. 28-pin part pinout (ssop) pin no. type pin name description cy8c28403, cy8c28413, cy8c28433, cy8c28445, and cy8c28452 28-pin psoc devices digital analog 1 i/o i, m, s p0[7] analog column mux and sar adc input. [8] 2 i/o i/o, m, s p0[5] analog column mux and sar adc input. analog column output. [8, 9] 3 i/o i/o, m, s p0[3] analog column mux and sar adc input. analog column output. [8, 9] 4 i/o i, m, s p0[1] analog column mux and sar adc input. [8] 5 i/o m p2[7] 6 i/o m p2[5] 7 i/o i, m p2[3] direct switched capacitor block input. [12] 8 i/o i, m p2[1] direct switched capacitor block input. [12] 9 output smp switch mode pump (smp) connection to external components. 10 i/o m p1[7] i2c0 serial clock (scl). 11 i/o m p1[5] i2c0 serial data (sda). 12 i/o m p1[3] 13 i/o m p1[1] crystal input (xtalin), i2c0 serial clock (scl), issp-sclk [7] . 14 power v ss ground connection. 15 i/o m p1[0] crystal output (xtalout), i2c0 serial data (sda), issp-sdata [7] . 16 i/o m p1[2] i2c1 serial data (sda). [10] 17 i/o m p1[4] optional external clock input (extclk). 18 i/o m p1[6] i2c1 serial clock (scl). [10] 19 input xres active high exter nal reset with internal pull-down. 20 i/o i, m p2[0] direct switched capacitor block input. [13] 21 i/o i, m p2[2] direct switched capacitor block input. [13] 22 i/o m p2[4] external analog ground (agnd). 23 i/o m p2[6] external voltage reference (vref). 24 i/o i, m, s p0[0] analog column mux and sar adc input. [8] 25 i/o i/o, m, s p0[2] analog column mux and sar adc input. analog column output. [8, 11] 26 i/o i/o, m, s p0[4] analog column mux and sar adc input. analog column output. [8, 11] 27 i/o i, m, s p0[6] analog column mux and sar adc input. [8] 28 power v dd supply voltage. legend : a = analog, i = input, o = output, s = sar adc input, and m = analog mux bus input ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vdd p0[6], m, ai, s p0[4], m, aio, s p0[2], m, aio, s p0[0], m, ai, s p2[6], m, external vref p2[4], m, external agnd p2[2], m, ai p2[0], m, ai xres p1[6], m, i2c1 scl p1[4], m, extclk p1[2], m, i2c1 sda p1[0], m, xtalout, i2c0 sda s, ai, m, p0[7] s, aio, m, p0[5] s, aio, m, p0[3] s, ai, m, p0[1] m, p2[7] m, p2[5] ai, m, p2[3] ai, m, p2[1] smp i2c0 scl, m, p1[7] i2c0 sda, m, p1[5] m, p1[3] i2c0 scl, xtalin, m, p1[1] vss notes 12. this pin is not a direct switched capacitor block analog input for cy8c28x03 and cy8c28x13 devices. 13. this pin is not a direct switched capacitor block analog input for cy8c28x03, cy8c28x13, cy8c 28x23, and cy8c28x33 devices.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 13 of 80 44-pin part pinout table 5. 44-pin part pinout (tqfp) pin no. type pin name description cy8c28513, CY8C28533, and cy8c28545 44-pin psoc devices digital analog 1 i/o m p2[5] 2 i/o i, m p2[3] direct switched capacitor block input. [12] 3 i/o i, m p2[1] direct switched capacitor block input. [12] 4 i/o m p4[7] 5 i/o m p4[5] 6 i/o m p4[3] 7 i/o m p4[1] 8 output smp switch mode pump (smp) connection to external components. 9 i/o m p3[7] 10 i/o m p3[5] 11 i/o m p3[3] 12 i/o m p3[1] 13 i/o m p1[7] i2c0 serial clock (scl). 14 i/o m p1[5] i2c0 serial data (sda). 15 i/o m p1[3] 16 i/o m p1[1] crystal input (xtalin), i2c0 serial clock (scl), issp-sclk [7] . 17 power v ss ground connection. 18 i/o m p1[0] crystal output (xtalout), i2c0 serial data (sda), issp-sdata [7] . 19 i/o m p1[2] i2c1 serial data (sda). [10] 20 i/o m p1[4] optional external clock input (extclk). 21 i/o m p1[6] i2c1 serial clock (scl). [10] 22 i/o m p3[0] i2c1 serial data (sda). [10] 23 i/o m p3[2] i2c1 serial clock (scl). [10] 24 i/o m p3[4] 25 i/o m p3[6] 26 input xres active high external reset with internal pull-down. 27 i/o m p4[0] 28 i/o m p4[2] 29 i/o m p4[4] 30 i/o m p4[6] 31 i/o i, m p2[0] direct switched capacitor block input. [13] 32 i/o i, m p2[2] direct switched capacitor block input. [13] 33 i/o m p2[4] external analog ground (agnd). 34 i/o m p2[6] external voltage reference (vref). 35 i/o i, m, s p0[0] analog column mux and sar adc input. [8] 36 i/o i/o, m s p0[2] analog column mux and sar adc input. analog column output. [8, 11] 37 i/o i/o, m, s p0[4] analog column mux and sar adc input. analog column output. [8, 11] 38 i/o i, m, s p0[6] analog column mux and sar adc input. [8] 39 power v dd supply voltage. 40 i/o i, m, s p0[7] analog column mux and sar adc input. [8] 41 i/o i/o, m, s p0[5] analog column mux and sar adc input. analog column output. [8, 9] 42 i/o i/o, m, s p0[3] analog column mux and sar adc input. analog column output. [8, 9] 43 i/o i, m, s p0[1] analog column mux and sar adc input. [8] 44 i/o p2[7] legend : a = analog, i = input, o = output, s = sar adc input, and m = analog mux bus input. tqfp 44 43 42 41 40 39 38 37 36 35 34 13 14 15 16 17 18 19 20 21 22 12 1 2 3 4 5 6 7 8 9 10 11 m, p2[5] ai, m, p2[3] ai, m, p2[1] m, p4[7] m, p4[5] m, p4[3] m, p4[1] smp m, p3[7] m, p3[5] m, p3[3] m, p3[1] i2c0 scl, m, p1[7] i2c0 sda, m, p1[5] m, p1[3] i2c0 scl, xtalin, m, p1[1] vss i2c0 sda, xtalout, m, p1[0] i2c1 sda, m, p1[2] extclk, m, p1[4] i2c1 scl, m, p1[6] i2c1 sda, m, p3[0] p2[4], m, external agnd p2[2], m, ai p2[0], m, ai p4[6], m p4[4], m p4[2], m p4[0], m xres p3[6], m p3[4], m p3[2], m, i2c1 scl p2[7], m p0[1], m, ai, s p0[3], m, aio, s p0[5], m, aio, s p0[7], m, ai, s vdd p0[6], m, ai, s p0[4], m, aio, s p0[2], m, aio, s p0[0], m, ai, s p2[6], m, external vref 33 32 31 30 29 28 27 26 25 24 23
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 14 of 80 48-pin part pinout table 6. 48-pin part pinout (qfn [14] ) pin no. type pin name description cy8c28623, cy8c28643, and cy8c28645 48-pin psoc devices digital analog 1 i/o i, m p2[3] direct switched capacitor block input. [12] 2 i/o i, m p2[1] direct switched capacitor block input. [12] 3 i/o m p4[7] 4 i/o m p4[5] 5 i/o m p4[3] 6 i/o m p4[1] 7 output smp switch mode pump (smp) connection to external components. 8 i/o m p3[7] 9 i/o m p3[5] 10 i/o m p3[3] 11 i/o m p3[1] 12 i/o m p5[3] 13 i/o m p5[1] 14 i/o m p1[7] i2c0 serial clock (scl). 15 i/o m p1[5] i2c0 serial data (sda). 16 i/o m p1[3] 17 i/o m p1[1] crystal input (xtalin), i2c0 serial clock (scl), issp-sclk [7] . 18 power v ss ground connection. 19 i/o m p1[0] crystal output (xtalout), i2c0 serial data (sda), issp-sdata [7] . 20 i/o m p1[2] i2c1 serial data (sda). [10] 21 i/o m p1[4] optional external clock input (extclk). 22 i/o m p1[6] i2c1 serial clock (scl). [10] 23 i/o m p5[0] 24 i/o m p5[2] 25 i/o m p3[0] i2c1 serial data (sda). [10] 26 i/o m p3[2] i2c1 serial clock (scl). [10] 27 i/o m p3[4] 28 i/o m p3[6] 29 input xres active high external reset with internal pull-down. 30 i/o m p4[0] 31 i/o m p4[2] pin no. type pin nam e description 32 i/o m p4[4] digital analog 33 i/o m p4[6] 41 i/o i, m, s p0[6] analog column mux and sar adc input. [8] 34 i/o i, m p2[0] direct switched capacitor block input. [13] 42 power v dd supply voltage. 35 i/o i, m p2[2] direct switched capacitor block input. [13] 43 i/o i, m, s p0[7] analog column mux and sar adc input. [8] 36 i/o m p2[4] external analog ground (agnd). 44 i/o i/o, m, s p0[5] analog column mux and sar adc input. analog column output. [8, 9] 37 i/o m p2[6] external voltage reference (vref). 45 i/o i/o, m, s p0[3] analog column mux and sar adc input. analog column output. [8, 9] 38 i/o i, m, s p0[0] analog column mux and sar adc input. [8] 46 i/o i, m, s p0[1] analog column mux and sar adc input. [8] 39 i/o i/o, m, s p0[2] analog column mux and sar adc input. analog column output. [8, 11] 47 i/o m p2[7] 40 i/o i/o, m, s p0[4] analog column mux and sar adc input. analog column output. [8, 11] 48 i/o m p2[5] legend : a = analog, i = input, o = output, s = sar adc input, and m = analog mux bus input. 13 14 15 16 17 18 19 20 21 22 23 24 p2[5], m p2[7], m p0[1], m, ai, s p0[3], m, aio, s p0[5], m, aio, s p0[7], m, ai, s vdd p0[6], m, ai, s p0[4], m, aio, s p0[2], m, aio, s p0[0], m, ai, s p2[6], m, external vref m, p5[1] i2c0 scl, m, p1[7] i2c0 sda, m, p1[5] m, p1[3] i2c0 scl, xtalin, m, p1[1] vss i2c0 sda, xtalout, m, p1[0] i2c1 sda, m, p1[2] extclk, m, p1[4] i2c1 scl, m, p1[6] m, p5[0] m, p5[2] ai, m, p2[3] ai, m, p2[1] m, p4[7] m, p4[5] m, p4[3] m, p4[1] smp m, p3[7] m, p3[5] m, p3[3] m, p3[1] m, p5[3] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 10 11 12 1 2 3 4 5 6 7 8 9 qfn (top view) p2[2], m, ai p2[0], m, ai p4[6], m p4[4], m p4[2], m p4[0], m xres p3[6], m p3[4], m p3[2], m, i2c1 scl p3[0], m, i2c1 sda p2[4], m, external agnd note 14. the qfn package has a center pad that must be connected to ground ( v ss )
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 15 of 80 56-pin part pinout the 56-pin ssop part is for the cy8c28000 on-chip debug (ocd) psoc device. note this part is only used for in-circuit debugging. it is not available for production. table 7. 56-pin part pinout (ssop) pin no. type pin name description cy8c28000 56-pin psoc device not for production digital analog 1 nc no connection. 2 i/o i, m, s p0[7] analog column mux and sar adc input. 3 i/o i/o, m, s p0[5] analog column mux and sar adc input. analog column output. 4 i/o i/o, m, s p0[3] analog column mux and sar adc input. analog column output. 5 i/o i, m, s p0[1] analog column mux and sar adc input. 6 i/o mp2[7] 7 i/o mp2[5] 8 i/o i p2[3] direct switched capacitor block input. 9 i/o i p2[1] direct switched capacitor block input. 10 i/o mp4[7] 11 i/o mp4[5] 12 i/o i, m p4[3] 13 i/o i, m p4[1] 14 ocd m ocde ocd even data i/o. 15 ocd m ocdo ocd odd data output. 16 output smp switch mode pump (smp) connection to required external components. 17 i/o mp3[7] 18 i/o mp3[5] 19 i/o mp3[3] 20 i/o mp3[1] 21 i/o mp5[3] 22 i/o mp5[1] 23 i/o m p1[7] i2c0 serial clock (scl). 24 i/o m p1[5] i2c0 serial data (sda). 25 nc no connection. 26 i/o mp1[3] 27 i/o m p1[1] crystal input (xtalin), i2c0 serial clock (scl), issp-sclk [7] . 28 power v ss ground connection. 29 nc no connection. 30 nc no connection. 31 i/o m p1[0] crystal output (xtalout), i2c0 serial data (sda), issp-sdata [7] . 32 i/o m p1[2] i2c1 serial data (sda). 33 i/o m p1[4] optional external clock input (extclk). 34 i/o mp1[6] i2c1 serial clock (scl). 35 i/o mp5[0] 36 i/o mp5[2] 37 i/o m p3[0] i2c1 serial data (sda). 38 i/o m p3[2] i2c1 serial clock (scl). 39 i/o mp3[4] 40 i/o mp3[6] ssop 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 nc ocde ocdo smp i2c0 scl, m, p1[7] nc vss s, ai, m, p0[7] s, aio, m, p0[5] s, aio, m, p0[3] ai, m, p2[3] s, ai, m, p0[1] m, p2[5] m, p2[7] ai, m, p2[1] m, p4[7] m, p4[5] m, p4[3] m, p4[1] m, p3[7] m, p5[1] m, p5[3] m, p3[1] m, p3[3] m, p3[5] i2c0 sda, m, p1[5] m, p1[3] sclk, i2c0 scl, xtalin, m, p1[1] vdd cclk hclk xres nc nc p1[6], m, i2c1 scl p1[2], m, i2c1 sda p0[6], m, ai, s p0[4], m, aio, s p0[2], m, aio, s p2[2], m, ai p0[0], m, ai, s p2[4], m, external agnd p2[6], m, external vref p2[0], m, ai p4[6], m p4[4], m p4[2], m p4[0], m p3[6], m p5[0], m p5[2], m p3[0], m, i2c1 sda p3[2], m, i2c1 scl p3[4], m p1[4], m, extclk p1[0], m, xtalout, i2c0 sda, sdata
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 16 of 80 pin no. type pin name description digital analog 41 input xres active high external reset with internal pull-down. 42 ocd m hclk ocd high speed clock output. 43 ocd m cclk ocd cpu clock output. 44 i/o mp4[0] 45 i/o mp4[2] 46 i/o mp4[4] 47 i/o mp4[6] 48 i/o i, m p2[0] direct switched capacitor block input. 49 i/o i, m p2[2] direct switched capacitor block input. 50 i/o m p2[4] external analog ground (agnd). 51 i/o m p2[6] external voltage reference (vref). 52 i/o i, m, s p0[0] analog column mux and sar adc input. 53 i/o i/o, m, s p0[2] analog column mux and sar adc input. analog column output. 54 i/o i/o, m, s p0[4] analog column mux and sar adc input. analog column output. 55 i/o i, m, s p0[6] analog column mux and sar adc input. 56 power v dd supply voltage. legend : a = analog, i = input, o = output, s = sar adc input, m = analog mux bus input, and ocd = on-chip debug. table 7. 56-pin part pinout (ssop) (continued)
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 17 of 80 register reference this section lists the registers of the cy8c28xxx psoc devices. for detailed register informati on, reference the psoc technical reference manual for cy8c28xxx psoc devices. register conventions the register conventions specific to this section are listed in the following table. register mapping tables cy8c28xxx psoc devices have a total register address space of 512 bytes. the register space is referred to as i/o space and is divided into two banks. the xio bit in the flag register (cpu_f) determines which bank of registers cpu instructions access. when the xio bit is set the registers in bank 1 are accessed by cpu instructions. when the xio bit is cleared the registers in bank 0 are accessed by cpu instructions. note in the following register mapping tables, blank fields are reserved and should not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 18 of 80 table 8. cy8c28x03 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbc20dr0 40 # 80 rdi2ri c0 rw prt0ie 01 rw dbc20dr1 41 w 81 rdi2syn c1 rw prt0gs 02 rw dbc20dr2 42 rw 82 rdi2is c2 rw prt0dm2 03 rw dbc20cr0 43 # 83 rdi2lt0 c3 rw prt1dr 04 rw dbc21dr0 44 # 84 rdi2lt1 c4 rw prt1ie 05 rw dbc21dr1 45 w 85 rdi2ro0 c5 rw prt1gs 06 rw dbc21dr2 46 rw 86 rdi2ro1 c6 rw prt1dm2 07 rw dbc21cr0 47 # 87 rdi2dsm c7 rw prt2dr 08 rw dcc22dr0 48 # 88 c8 prt2ie 09 rw dcc22dr1 49 w 89 c9 prt2gs 0a rw dcc22dr2 4a rw 8a ca prt2dm2 0b rw dcc22cr0 4b # 8b cb prt3dr 0c rw dcc23dr0 4c # 8c cc prt3ie 0d rw dcc23dr1 4d w 8d cd prt3gs 0e rw dcc23dr2 4e rw 8e ce prt3dm2 0f rw dcc23cr0 4f # 8f cf prt4dr 10 rw 50 90 cur_pp d0 rw prt4ie 11 rw 51 91 stk_pp d1 rw prt4gs 12 rw 52 92 d2 prt4dm2 13 rw 53 93 idx_pp d3 rw prt5dr 14 rw 54 94 mvr_pp d4 rw prt5ie 15 rw 55 95 mvw_pp d5 rw prt5gs 16 rw 56 96 i2c0_cfg d6 rw prt5dm2 17 rw 57 97 i2c0_scr d7 # 18 58 98 i2c0_dr d8 rw 19 59 99 i2c0_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c int_clr2 dc rw 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f int_msk2 df rw dbc00dr0 20 # 60 a0 int_msk0 e0 rw dbc00dr1 21 w 61 a1 int_msk1 e1 rw dbc00dr2 22 rw 62 a2 int_vc e2 rc dbc00cr0 23 # 63 a3 res_wdt e3 w dbc01dr0 24 # 64 a4 i2c1_scr e4 # dbc01dr1 25 w 65 a5 i2c1_mscr e5 # dbc01dr2 26 rw 66 a6 e6 dbc01cr0 27 # i2c1_dr 67 rw a7 e7 dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw sadc_dh 6a rw mul1_dh aa r mul0_dh ea r dcc02cr0 2b # sadc_dl 6b rw mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # 70 rdi0ri b0 rw f0 dbc10dr1 31 w 71 rdi0syn b1 rw f1 dbc10dr2 32 rw 72 rdi0is b2 rw f2 dbc10cr0 33 # 73 rdi0lt0 b3 rw f3 dbc11dr0 34 # 74 rdi0lt1 b4 rw f4 dbc11dr1 35 w 75 rdi0ro0 b5 rw f5 dbc11dr2 36 rw 76 rdi0ro1 b6 rw f6 dbc11cr0 37 # 77 rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # 78 rdi1ri b8 rw f8 dcc12dr1 39 w 79 rdi1syn b9 rw f9 dcc12dr2 3a rw 7a rdi1is ba rw fa dcc12cr0 3b # 7b rdi1lt0 bb rw fb dcc13dr0 3c # 7c rdi1lt1 bc rw fc dcc13dr1 3d w 7d rdi1ro0 bd rw fd dcc13dr2 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 19 of 80 table 9. cy8c28x03 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbc20fn 40 rw 80 rdi2ri c0 rw prt0dm1 01 rw dbc20in 41 rw sadc_tscmpl 81 rw rdi2syn c1 rw prt0ic0 02 rw dbc20ou 42 rw sadc_tscmph 82 rw rdi2is c2 rw prt0ic1 03 rw dbc20cr1 43 rw 83 rdi2lt0 c3 rw prt1dm0 04 rw dbc21fn 44 rw 84 rdi2lt1 c4 rw prt1dm1 05 rw dbc21in 45 rw 85 rdi2ro0 c5 rw prt1ic0 06 rw dbc21ou 46 rw 86 rdi2ro1 c6 rw prt1ic1 07 rw dbc21cr1 47 rw 87 rdi2dsm c7 rw prt2dm0 08 rw dcc22fn 48 rw 88 c8 prt2dm1 09 rw dcc22in 49 rw 89 c9 prt2ic0 0a rw dcc22ou 4a rw 8a ca prt2ic1 0b rw dcc22cr1 4b rw 8b cb prt3dm0 0c rw dcc23fn 4c rw 8c cc prt3dm1 0d rw dcc23in 4d rw 8d cd prt3ic0 0e rw dcc23ou 4e rw 8e ce prt3ic1 0f rw dcc23cr1 4f rw 8f cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 91 gdi_e_in d1 rw prt4ic0 12 rw 52 92 gdi_o_ou d2 rw prt4ic1 13 rw 53 93 gdi_e_ou d3 rw prt5dm0 14 rw 54 94 d4 prt5dm1 15 rw 55 95 d5 prt5ic0 16 rw 56 96 d6 prt5ic1 17 rw 57 97 d7 18 58 98 d8 19 59 99 d9 1a 5a 9a da 1b 5b 9b db 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw 60 gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw 61 gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw 62 gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw 63 gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw 64 rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw 65 rtc_m a5 rw e5 dbc01ou 26 rw 66 rtc_s a6 rw e6 dbc01cr1 27 rw 67 rtc_cr a7 rw e7 dcc02fn 28 rw 68 sadc_cr0 a8 rw imo_tr e8 rw dcc02in 29 rw 69 sadc_cr1 a9 rw ilo_tr e9 rw dcc02ou 2a rw 6a sadc_cr2 aa rw bdg_tr ea rw dcc02cr1 2b rw i2c1_cfg 6b rw sadc_cr3 ab rw eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw ec dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw ed dcc03ou 2e rw tmp_dr2 6e rw i2c1_addr ae rw ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw sadc_tscr0 71 rw rdi0syn b1 rw f1 dbc10ou 32 rw sadc_tscr1 72 rw rdi0is b2 rw f2 dbc10cr1 33 rw 73 rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rdi0lt1 b4 rw f4 dbc11in 35 rw 75 rdi0ro0 b5 rw f5 dbc11ou 36 rw 76 rdi0ro1 b6 rw f6 dbc11cr1 37 rw 77 rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw 79 rdi1syn b9 rw f9 dcc12ou 3a rw 7a rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw 7b rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw 7d rdi1ro0 bd rw fd dcc13ou 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 20 of 80 table 10. cy8c28x13 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbc20dr0 40 # 80 rdi2ri c0 rw prt0ie 01 rw dbc20dr1 41 w 81 rdi2syn c1 rw prt0gs 02 rw dbc20dr2 42 rw 82 rdi2is c2 rw prt0dm2 03 rw dbc20cr0 43 # 83 rdi2lt0 c3 rw prt1dr 04 rw dbc21dr0 44 # 84 rdi2lt1 c4 rw prt1ie 05 rw dbc21dr1 45 w 85 rdi2ro0 c5 rw prt1gs 06 rw dbc21dr2 46 rw 86 rdi2ro1 c6 rw prt1dm2 07 rw dbc21cr0 47 # 87 rdi2dsm c7 rw prt2dr 08 rw dcc22dr0 48 # 88 c8 prt2ie 09 rw dcc22dr1 49 w 89 c9 prt2gs 0a rw dcc22dr2 4a rw 8a ca prt2dm2 0b rw dcc22cr0 4b # 8b cb prt3dr 0c rw dcc23dr0 4c # 8c cc prt3ie 0d rw dcc23dr1 4d w 8d cd prt3gs 0e rw dcc23dr2 4e rw 8e ce prt3dm2 0f rw dcc23cr0 4f # 8f cf prt4dr 10 rw 50 90 cur_pp d0 rw prt4ie 11 rw 51 91 stk_pp d1 rw prt4gs 12 rw 52 92 d2 prt4dm2 13 rw 53 93 idx_pp d3 rw prt5dr 14 rw 54 94 mvr_pp d4 rw prt5ie 15 rw 55 95 mvw_pp d5 rw prt5gs 16 rw 56 96 i2c0_cfg d6 rw prt5dm2 17 rw 57 97 i2c0_scr d7 # 18 58 98 i2c0_dr d8 rw 19 59 99 i2c0_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c int_clr2 dc rw 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f int_msk2 df rw dbc00dr0 20 # 60 dec0_dh a0 rc int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw dec0_dl a1 rc int_msk1 e1 rw dbc00dr2 22 rw 62 dec1_dh a2 rc int_vc e2 rc dbc00cr0 23 # 63 dec1_dl a3 rc res_wdt e3 w dbc01dr0 24 # 64 a4 e4 dbc01dr1 25 w 65 a5 e5 dbc01dr2 26 rw 66 a6 dec_cr0* e6 rw dbc01cr0 27 # 67 a7 dec_cr1* e7 rw dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw sadc_dh 6a rw mul1_dh aa r mul0_dh ea r dcc02cr0 2b # sadc_dl 6b rw mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # 70 rdi0ri b0 rw f0 dbc10dr1 31 w 71 rdi0syn b1 rw f1 dbc10dr2 32 rw 72 rdi0is b2 rw f2 dbc10cr0 33 # 73 rdi0lt0 b3 rw f3 dbc11dr0 34 # 74 rdi0lt1 b4 rw f4 dbc11dr1 35 w 75 rdi0ro0 b5 rw f5 dbc11dr2 36 rw 76 rdi0ro1 b6 rw f6 dbc11cr0 37 # 77 rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # 78 rdi1ri b8 rw f8 dcc12dr1 39 w 79 rdi1syn b9 rw f9 dcc12dr2 3a rw 7a rdi1is ba rw fa dcc12cr0 3b # 7b rdi1lt0 bb rw fb dcc13dr0 3c # 7c rdi1lt1 bc rw dac1_d fc rw dcc13dr1 3d w 7d rdi1ro0 bd rw dac0_d fd rw dcc13dr2 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 21 of 80 table 11. cy8c28x13 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbc20fn 40 rw 80 rdi2ri c0 rw prt0dm1 01 rw dbc20in 41 rw sadc_tscmpl 81 rw rdi2syn c1 rw prt0ic0 02 rw dbc20ou 42 rw sadc_tscmph 82 rw rdi2is c2 rw prt0ic1 03 rw dbc20cr1 43 rw ace_amd_cr1 83 rw rdi2lt0 c3 rw prt1dm0 04 rw dbc21fn 44 rw 84 rdi2lt1 c4 rw prt1dm1 05 rw dbc21in 45 rw ace_pwm_cr 85 rw rdi2ro0 c5 rw prt1ic0 06 rw dbc21ou 46 rw ace_adc0_cr 86 rw rdi2ro1 c6 rw prt1ic1 07 rw dbc21cr1 47 rw ace_adc1_cr 87 rw rdi2dsm c7 rw prt2dm0 08 rw dcc22fn 48 rw 88 c8 prt2dm1 09 rw dcc22in 49 rw ace_clk_cr0 89 rw c9 prt2ic0 0a rw dcc22ou 4a rw ace_clk_cr1 8a rw ca prt2ic1 0b rw dcc22cr1 4b rw ace_clk_cr3 8b rw cb prt3dm0 0c rw dcc23fn 4c rw 8c rw cc prt3dm1 0d rw dcc23in 4d rw ace01cr1 8d rw cd prt3ic0 0e rw dcc23ou 4e rw ace01cr2 8e rw ce prt3ic1 0f rw dcc23cr1 4f rw ase11cr0 8f rw cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 dec0_cr0 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 dec_cr3 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 93 gdi_e_ou d3 rw prt5dm0 14 rw 54 94 dec0_cr d4 rw prt5dm1 15 rw 55 dec1_cr0 95 rw dec1_cr d5 rw prt5ic0 16 rw 56 96 d6 prt5ic1 17 rw 57 97 d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a dec_cr5 9a rw mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c idac_cr1 dc rw 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw 60 gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw 61 gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw 62 gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw 63 gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw 64 rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw 65 rtc_m a5 rw adc0_tr e5 rw dbc01ou 26 rw 66 rtc_s a6 rw adc1_tr e6 rw dbc01cr1 27 rw 67 rtc_cr a7 rw idac_cr2 e7 rw dcc02fn 28 rw 68 sadc_cr0 a8 rw imo_tr e8 rw dcc02in 29 rw 69 sadc_cr1 a9 rw ilo_tr e9 rw dcc02ou 2a rw amux_cfg1 6a rw sadc_cr2 aa rw bdg_tr ea rw dcc02cr1 2b rw 6b sadc_cr3 ab rw eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw mux_cr5 ed rw dcc03ou 2e rw tmp_dr2 6e rw ae ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw sadc_tscr0 71 rw rdi0syn b1 rw f1 dbc10ou 32 rw sadc_tscr1 72 rw rdi0is b2 rw f2 dbc10cr1 33 rw ace_amd_cr0 73 rw rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rw rdi0lt1 b4 rw f4 dbc11in 35 rw ace_amx_in 75 rw rdi0ro0 b5 rw f5 dbc11ou 36 rw ace_cmp_cr0 76 rw rdi0ro1 b6 rw f6 dbc11cr1 37 rw ace_cmp_cr1 77 rw rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw ace_cmp_gi_en 79 rw rdi1syn b9 rw f9 dcc12ou 3a rw ace_alt_cr0 7a rw rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw ace_abf_cr0 7b rw rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw ace0_cr1 7d rw rdi1ro0 bd rw idac_cr0 fd rw dcc13ou 3e rw ace0_cr2 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw ace0_cr3 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 22 of 80 table 12. cy8c28x23 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbc20dr0 40 # asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw dbc20dr1 41 w asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw dbc20dr2 42 rw asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw dbc20cr0 43 # asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw dbc21dr0 44 # asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw dbc21dr1 45 w asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw dbc21dr2 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw dbc21cr0 47 # asd11cr3 87 rw rdi2dsm c7 rw prt2dr 08 rw dcc22dr0 48 # 88 c8 prt2ie 09 rw dcc22dr1 49 w 89 c9 prt2gs 0a rw dcc22dr2 4a rw 8a ca prt2dm2 0b rw dcc22cr0 4b # 8b cb prt3dr 0c rw dcc23dr0 4c # 8c cc prt3ie 0d rw dcc23dr1 4d w 8d cd prt3gs 0e rw dcc23dr2 4e rw 8e ce prt3dm2 0f rw dcc23cr0 4f # 8f cf prt4dr 10 rw 50 asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw 51 asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw 52 asd20cr2 92 rw d2 prt4dm2 13 rw 53 asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw 54 asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw 55 asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw 56 asc21cr2 96 rw i2c0_cfg d6 rw prt5dm2 17 rw 57 asc21cr3 97 rw i2c0_scr d7 # 18 58 98 i2c0_dr d8 rw 19 59 99 i2c0_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c int_clr2 dc rw 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f int_msk2 df rw dbc00dr0 20 # amx_in 60 rw dec0_dh a0 rc int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw dec0_dl a1 rc int_msk1 e1 rw dbc00dr2 22 rw clk_cr3 62 rw dec1_dh a2 rc int_vc e2 rc dbc00cr0 23 # arf_cr 63 rw dec1_dl a3 rc res_wdt e3 w dbc01dr0 24 # cmp_cr0 64 # a4 i2c1_scr e4 # dbc01dr1 25 w asy_cr 65 # a5 i2c1_mscr e5 # dbc01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0* e6 rw dbc01cr0 27 # i2c1_dr 67 rw a7 dec_cr1* e7 rw dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcc02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbc10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbc10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbc10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbc11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbc11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbc11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbc11cr0 37 # acb01cr2 77 rw rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # 78 rdi1ri b8 rw f8 dcc12dr1 39 w 79 rdi1syn b9 rw f9 dcc12dr2 3a rw 7a rdi1is ba rw fa dcc12cr0 3b # 7b rdi1lt0 bb rw fb dcc13dr0 3c # 7c rdi1lt1 bc rw fc dcc13dr1 3d w 7d rdi1ro0 bd rw fd dcc13dr2 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 23 of 80 table 13. cy8c28x23 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbc20fn 40 rw 80 rdi2ri c0 rw prt0dm1 01 rw dbc20in 41 rw 81 rdi2syn c1 rw prt0ic0 02 rw dbc20ou 42 rw 82 rdi2is c2 rw prt0ic1 03 rw dbc20cr1 43 rw 83 rdi2lt0 c3 rw prt1dm0 04 rw dbc21fn 44 rw 84 rdi2lt1 c4 rw prt1dm1 05 rw dbc21in 45 rw 85 rdi2ro0 c5 rw prt1ic0 06 rw dbc21ou 46 rw 86 rdi2ro1 c6 rw prt1ic1 07 rw dbc21cr1 47 rw 87 rdi2dsm c7 rw prt2dm0 08 rw dcc22fn 48 rw 88 c8 prt2dm1 09 rw dcc22in 49 rw 89 c9 prt2ic0 0a rw dcc22ou 4a rw 8a ca prt2ic1 0b rw dcc22cr1 4b rw 8b cb prt3dm0 0c rw dcc23fn 4c rw 8c cc prt3dm1 0d rw dcc23in 4d rw 8d cd prt3ic0 0e rw dcc23ou 4e rw 8e ce prt3ic1 0f rw dcc23cr1 4f rw 8f cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 dec0_cr0 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 dec_cr3 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 93 rw gdi_e_ou d3 rw prt5dm0 14 rw 54 94 rw dec0_cr d4 rw prt5dm1 15 rw 55 dec1_cr0 95 rw dec1_cr d5 rw prt5ic0 16 rw 56 96 d6 prt5ic1 17 rw 57 97 d7 18 58 98 d8 19 59 99 d9 1a 5a dec_cr5 9a rw da 1b 5b 9b db 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw clk_cr0 60 rw gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw clk_cr1 61 rw gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw abf_cr0 62 rw gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw amd_cr0 63 rw gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw cmp_go_en 64 rw rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw 65 rtc_m a5 rw e5 dbc01ou 26 rw amd_cr1 66 rw rtc_s a6 rw e6 dbc01cr1 27 rw alt_cr0 67 rw rtc_cr a7 rw e7 dcc02fn 28 rw 68 a8 imo_tr e8 rw dcc02in 29 rw clk_cr2 69 rw a9 ilo_tr e9 rw dcc02ou 2a rw 6a aa bdg_tr ea rw dcc02cr1 2b rw i2c1_cfg 6b rw ab eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw ac ec dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw ed dcc03ou 2e rw tmp_dr2 6e rw i2c1_addr ae rw ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw 71 rdi0syn b1 rw f1 dbc10ou 32 rw 72 rdi0is b2 rw f2 dbc10cr1 33 rw 73 rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rdi0lt1 b4 rw f4 dbc11in 35 rw 75 rdi0ro0 b5 rw f5 dbc11ou 36 rw 76 rdi0ro1 b6 rw f6 dbc11cr1 37 rw 77 rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw 79 rdi1syn b9 rw f9 dcc12ou 3a rw 7a rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw 7b rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw 7d rdi1ro0 bd rw fd dcc13ou 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 24 of 80 table 14. cy8c28x33 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbc20dr0 40 # asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw dbc20dr1 41 w asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw dbc20dr2 42 rw asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw dbc20cr0 43 # asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw dbc21dr0 44 # asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw dbc21dr1 45 w asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw dbc21dr2 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw dbc21cr0 47 # asd11cr3 87 rw rdi2dsm c7 rw prt2dr 08 rw dcc22dr0 48 # 88 c8 prt2ie 09 rw dcc22dr1 49 w 89 c9 prt2gs 0a rw dcc22dr2 4a rw 8a ca prt2dm2 0b rw dcc22cr0 4b # 8b cb prt3dr 0c rw dcc23dr0 4c # 8c cc prt3ie 0d rw dcc23dr1 4d w 8d cd prt3gs 0e rw dcc23dr2 4e rw 8e ce prt3dm2 0f rw dcc23cr0 4f # 8f cf prt4dr 10 rw 50 asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw 51 asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw 52 asd20cr2 92 rw d2 prt4dm2 13 rw 53 asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw 54 asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw 55 asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw 56 asc21cr2 96 rw i2c0_cfg d6 rw prt5dm2 17 rw 57 asc21cr3 97 rw i2c0_scr d7 # 18 58 98 i2c0_dr d8 rw 19 59 99 i2c0_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c int_clr2 dc rw 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f int_msk2 df rw dbc00dr0 20 # amx_in 60 rw dec0_dh a0 rc int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw dec0_dl a1 rc int_msk1 e1 rw dbc00dr2 22 rw clk_cr3 62 rw dec1_dh a2 rc int_vc e2 rc dbc00cr0 23 # arf_cr 63 rw dec1_dl a3 rc res_wdt e3 w dbc01dr0 24 # cmp_cr0 64 # dec2_dh a4 rc e4 dbc01dr1 25 w asy_cr 65 # dec2_dl a5 rc e5 dbc01dr2 26 rw cmp_cr1 66 rw dec3_dh a6 rc dec_cr0* e6 rw dbc01cr0 27 # 67 dec3_dl a7 rc dec_cr1* e7 rw dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw sadc_dh 6a rw mul1_dh aa r mul0_dh ea r dcc02cr0 2b # sadc_dl 6b rw mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbc10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbc10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbc10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbc11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbc11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbc11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbc11cr0 37 # acb01cr2 77 rw rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # 78 rdi1ri b8 rw f8 dcc12dr1 39 w 79 rdi1syn b9 rw f9 dcc12dr2 3a rw 7a rdi1is ba rw fa dcc12cr0 3b # 7b rdi1lt0 bb rw fb dcc13dr0 3c # 7c rdi1lt1 bc rw dac1_d fc rw dcc13dr1 3d w 7d rdi1ro0 bd rw dac0_d fd rw dcc13dr2 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 25 of 80 table 15. cy8c28x33 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbc20fn 40 rw 80 rdi2ri c0 rw prt0dm1 01 rw dbc20in 41 rw sadc_tscmpl 81 rw rdi2syn c1 rw prt0ic0 02 rw dbc20ou 42 rw sadc_tscmph 82 rw rdi2is c2 rw prt0ic1 03 rw dbc20cr1 43 rw ace_amd_cr1 83 rw rdi2lt0 c3 rw prt1dm0 04 rw dbc21fn 44 rw 84 rdi2lt1 c4 rw prt1dm1 05 rw dbc21in 45 rw ace_pwm_cr 85 rw rdi2ro0 c5 rw prt1ic0 06 rw dbc21ou 46 rw ace_adc0_cr 86 rw rdi2ro1 c6 rw prt1ic1 07 rw dbc21cr1 47 rw ace_adc1_cr 87 rw rdi2dsm c7 rw prt2dm0 08 rw dcc22fn 48 rw 88 rw c8 prt2dm1 09 rw dcc22in 49 rw ace_clk_cr0 89 rw c9 prt2ic0 0a rw dcc22ou 4a rw ace_clk_cr1 8a rw ca prt2ic1 0b rw dcc22cr1 4b rw ace_clk_cr3 8b rw cb prt3dm0 0c rw dcc23fn 4c rw 8c cc prt3dm1 0d rw dcc23in 4d rw ace01cr1 8d rw cd prt3ic0 0e rw dcc23ou 4e rw ace01cr2 8e rw ce prt3ic1 0f rw dcc23cr1 4f rw ase11cr0 8f rw cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 dec0_cr0 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 dec_cr3 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 93 gdi_e_ou d3 rw prt5dm0 14 rw 54 94 dec0_cr d4 rw prt5dm1 15 rw 55 dec1_cr0 95 rw dec1_cr d5 rw prt5ic0 16 rw 56 dec_cr4 96 rw dec2_cr d6 rw prt5ic1 17 rw 57 97 dec3_cr d7 rw 18 58 98 mux_cr0 d8 rw 19 59 dec2_cr0 99 rw mux_cr1 d9 rw 1a 5a dec_cr5 9a rw mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c idac_cr1 dc rw 1d 5d dec3_cr0 9d rw osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw clk_cr0 60 rw gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw clk_cr1 61 rw gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw abf_cr0 62 rw gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw amd_cr0 63 rw gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw cmp_go_en 64 rw rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw 65 rtc_m a5 rw adc0_tr e5 rw dbc01ou 26 rw amd_cr1 66 rw rtc_s a6 rw adc1_tr e6 rw dbc01cr1 27 rw alt_cr0 67 rw rtc_cr a7 rw idac_cr2 e7 rw dcc02fn 28 rw 68 sadc_cr0 a8 rw imo_tr e8 rw dcc02in 29 rw clk_cr2 69 rw sadc_cr1 a9 rw ilo_tr e9 rw dcc02ou 2a rw amux_cfg1 6a rw sadc_cr2 aa rw bdg_tr ea rw dcc02cr1 2b rw 6b sadc_cr3 ab rw eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw mux_cr5 ed rw dcc03ou 2e rw tmp_dr2 6e rw ae ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw sadc_tscr0 71 rw rdi0syn b1 rw f1 dbc10ou 32 rw sadc_tscr1 72 rw rdi0is b2 rw f2 dbc10cr1 33 rw ace_amd_cr0 73 rw rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rdi0lt1 b4 rw f4 dbc11in 35 rw ace_amx_in 75 rw rdi0ro0 b5 rw f5 dbc11ou 36 rw ace_cmp_cr0 76 rw rdi0ro1 b6 rw f6 dbc11cr1 37 rw ace_cmp_cr1 77 rw rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw ace_cmp_gi_en 79 rw rdi1syn b9 rw f9 dcc12ou 3a rw ace_alt_cr0 7a rw rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw ace_abf_cr0 7b rw rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw ace0_cr1 7d rw rdi1ro0 bd rw idac_cr0 fd rw dcc13ou 3e rw ace0_cr2 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw ace0_cr3 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 26 of 80 table 16. cy8c28x43 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbc20dr0 40 # asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw dbc20dr1 41 w asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw dbc20dr2 42 rw asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw dbc20cr0 43 # asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw dbc21dr0 44 # asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw dbc21dr1 45 w asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw dbc21dr2 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw dbc21cr0 47 # asd11cr3 87 rw rdi2dsm c7 rw prt2dr 08 rw dcc22dr0 48 # asc12cr0 88 rw c8 prt2ie 09 rw dcc22dr1 49 w asc12cr1 89 rw c9 prt2gs 0a rw dcc22dr2 4a rw asc12cr2 8a rw ca prt2dm2 0b rw dcc22cr0 4b # asc12cr3 8b rw cb prt3dr 0c rw dcc23dr0 4c # asd13cr0 8c rw cc prt3ie 0d rw dcc23dr1 4d w asd13cr1 8d rw cd prt3gs 0e rw dcc23dr2 4e rw asd13cr2 8e rw ce prt3dm2 0f rw dcc23cr0 4f # asd13cr3 8f rw cf prt4dr 10 rw 50 asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw 51 asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw 52 asd20cr2 92 rw d2 prt4dm2 13 rw 53 asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw 54 asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw 55 asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw 56 asc21cr2 96 rw i2c0_cfg d6 rw prt5dm2 17 rw 57 asc21cr3 97 rw i2c0_scr d7 # 18 58 asd22cr0 98 rw i2c0_dr d8 rw 19 59 asd22cr1 99 rw i2c0_mscr d9 # 1a 5a asd22cr2 9a rw int_clr0 da rw 1b 5b asd22cr3 9b rw int_clr1 db rw 1c 5c asc23cr0 9c rw int_clr2 dc rw 1d 5d asc23cr1 9d rw int_clr3 dd rw 1e 5e asc23cr2 9e rw int_msk3 de rw 1f 5f asc23cr3 9f rw int_msk2 df rw dbc00dr0 20 # amx_in 60 rw dec0_dh a0 rc int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw dec0_dl a1 rc int_msk1 e1 rw dbc00dr2 22 rw clk_cr3 62 rw dec1_dh a2 rc int_vc e2 rc dbc00cr0 23 # arf_cr 63 rw dec1_dl a3 rc res_wdt e3 w dbc01dr0 24 # cmp_cr0 64 # dec2_dh a4 rc i2c1_scr e4 # dbc01dr1 25 w asy_cr 65 # dec2_dl a5 rc i2c1_mscr e5 # dbc01dr2 26 rw cmp_cr1 66 rw dec3_dh a6 rc dec_cr0* e6 rw dbc01cr0 27 # i2c1_dr 67 rw dec3_dl a7 rc dec_cr1* e7 rw dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw sadc_dh 6a rw mul1_dh aa r mul0_dh ea r dcc02cr0 2b # sadc_dl 6b rw mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbc10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbc10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbc10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbc11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbc11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbc11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbc11cr0 37 # acb01cr2 77 rw rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcc12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcc12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcc12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcc13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw fc dcc13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw fd dcc13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # acb03cr2 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 27 of 80 table 17. cy8c28x43 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbc20fn 40 rw 80 rdi2ri c0 rw prt0dm1 01 rw dbc20in 41 rw sadc_tscmpl 81 rw rdi2syn c1 rw prt0ic0 02 rw dbc20ou 42 rw sadc_tscmph 82 rw rdi2is c2 rw prt0ic1 03 rw dbc20cr1 43 rw 83 rdi2lt0 c3 rw prt1dm0 04 rw dbc21fn 44 rw 84 rdi2lt1 c4 rw prt1dm1 05 rw dbc21in 45 rw 85 rdi2ro0 c5 rw prt1ic0 06 rw dbc21ou 46 rw 86 rdi2ro1 c6 rw prt1ic1 07 rw dbc21cr1 47 rw 87 rdi2dsm c7 rw prt2dm0 08 rw dcc22fn 48 rw 88 c8 prt2dm1 09 rw dcc22in 49 rw 89 c9 prt2ic0 0a rw dcc22ou 4a rw 8a ca prt2ic1 0b rw dcc22cr1 4b rw 8b cb prt3dm0 0c rw dcc23fn 4c rw 8c cc prt3dm1 0d rw dcc23in 4d rw 8d cd prt3ic0 0e rw dcc23ou 4e rw 8e ce prt3ic1 0f rw dcc23cr1 4f rw 8f cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 dec0_cr0 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 dec_cr3 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 93 gdi_e_ou d3 rw prt5dm0 14 rw 54 94 dec0_cr d4 rw prt5dm1 15 rw 55 dec1_cr0 95 rw dec1_cr d5 rw prt5ic0 16 rw 56 dec_cr4 96 rw dec2_cr d6 rw prt5ic1 17 rw 57 97 dec3_cr d7 rw 18 58 98 mux_cr0 d8 rw 19 59 dec2_cr0 99 rw mux_cr1 d9 rw 1a 5a dec_cr5 9a rw mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c dc 1d 5d dec3_cr0 9d rw osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw clk_cr0 60 rw gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw clk_cr1 61 rw gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw abf_cr0 62 rw gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw amd_cr0 63 rw gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw cmp_go_en 64 rw rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw cmp_go_en1 65 rw rtc_m a5 rw e5 dbc01ou 26 rw amd_cr1 66 rw rtc_s a6 rw e6 dbc01cr1 27 rw alt_cr0 67 rw rtc_cr a7 rw e7 dcc02fn 28 rw alt_cr1 68 rw sadc_cr0 a8 rw imo_tr e8 rw dcc02in 29 rw clk_cr2 69 rw sadc_cr1 a9 rw ilo_tr e9 rw dcc02ou 2a rw amux_cfg1 6a rw sadc_cr2 aa rw bdg_tr ea rw dcc02cr1 2b rw i2c1_cfg 6b rw sadc_cr3 ab rw eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw mux_cr5 ed rw dcc03ou 2e rw tmp_dr2 6e rw i2c1_addr ae rw ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw sadc_tscr0 71 rw rdi0syn b1 rw f1 dbc10ou 32 rw sadc_tscr1 72 rw rdi0is b2 rw f2 dbc10cr1 33 rw 73 rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rdi0lt1 b4 rw f4 dbc11in 35 rw 75 rdi0ro0 b5 rw f5 dbc11ou 36 rw 76 rdi0ro1 b6 rw f6 dbc11cr1 37 rw 77 rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw 79 rdi1syn b9 rw f9 dcc12ou 3a rw 7a rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw 7b rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw 7d rdi1ro0 bd rw fd dcc13ou 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 28 of 80 table 18. cy8c28x45 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbc20dr0 40 # asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw dbc20dr1 41 w asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw dbc20dr2 42 rw asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw dbc20cr0 43 # asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw dbc21dr0 44 # asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw dbc21dr1 45 w asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw dbc21dr2 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw dbc21cr0 47 # asd11cr3 87 rw rdi2dsm c7 rw prt2dr 08 rw dcc22dr0 48 # asc12cr0 88 rw c8 prt2ie 09 rw dcc22dr1 49 w asc12cr1 89 rw c9 prt2gs 0a rw dcc22dr2 4a rw asc12cr2 8a rw ca prt2dm2 0b rw dcc22cr0 4b # asc12cr3 8b rw cb prt3dr 0c rw dcc23dr0 4c # asd13cr0 8c rw cc prt3ie 0d rw dcc23dr1 4d w asd13cr1 8d rw cd prt3gs 0e rw dcc23dr2 4e rw asd13cr2 8e rw ce prt3dm2 0f rw dcc23cr0 4f # asd13cr3 8f rw cf prt4dr 10 rw 50 asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw 51 asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw 52 asd20cr2 92 rw d2 prt4dm2 13 rw 53 asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw 54 asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw 55 asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw 56 asc21cr2 96 rw i2c0_cfg d6 rw prt5dm2 17 rw 57 asc21cr3 97 rw i2c0_scr d7 # 18 58 asd22cr0 98 rw i2c0_dr d8 rw 19 59 asd22cr1 99 rw i2c0_mscr d9 # 1a 5a asd22cr2 9a rw int_clr0 da rw 1b 5b asd22cr3 9b rw int_clr1 db rw 1c 5c asc23cr0 9c rw int_clr2 dc rw 1d 5d asc23cr1 9d rw int_clr3 dd rw 1e 5e asc23cr2 9e rw int_msk3 de rw 1f 5f asc23cr3 9f rw int_msk2 df rw dbc00dr0 20 # amx_in 60 rw dec0_dh a0 rc int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw dec0_dl a1 rc int_msk1 e1 rw dbc00dr2 22 rw clk_cr3 62 rw dec1_dh a2 rc int_vc e2 rc dbc00cr0 23 # arf_cr 63 rw dec1_dl a3 rc res_wdt e3 w dbc01dr0 24 # cmp_cr0 64 # dec2_dh a4 rc i2c1_scr e4 # dbc01dr1 25 w asy_cr 65 # dec2_dl a5 rc i2c1_mscr e5 # dbc01dr2 26 rw cmp_cr1 66 rw dec3_dh a6 rc dec_cr0* e6 rw dbc01cr0 27 # i2c1_dr 67 rw dec3_dl a7 rc dec_cr1* e7 rw dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw sadc_dh 6a rw mul1_dh aa r mul0_dh ea r dcc02cr0 2b # sadc_dl 6b rw mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbc10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbc10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbc10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbc11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbc11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbc11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbc11cr0 37 # acb01cr2 77 rw rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcc12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcc12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcc12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcc13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw dac1_d fc rw dcc13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw dac0_d fd rw dcc13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # acb03cr2 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 29 of 80 table 19. cy8c28x45 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbc20fn 40 rw 80 rw rdi2ri c0 rw prt0dm1 01 rw dbc20in 41 rw sadc_tscmpl 81 rw rdi2syn c1 rw prt0ic0 02 rw dbc20ou 42 rw sadc_tscmph 82 rw rdi2is c2 rw prt0ic1 03 rw dbc20cr1 43 rw ace_amd_cr1 83 rw rdi2lt0 c3 rw prt1dm0 04 rw dbc21fn 44 rw 84 rw rdi2lt1 c4 rw prt1dm1 05 rw dbc21in 45 rw ace_pwm_cr 85 rw rdi2ro0 c5 rw prt1ic0 06 rw dbc21ou 46 rw ace_adc0_cr 86 rw rdi2ro1 c6 rw prt1ic1 07 rw dbc21cr1 47 rw ace_adc1_cr 87 rw rdi2dsm c7 rw prt2dm0 08 rw dcc22fn 48 rw 88 rw c8 prt2dm1 09 rw dcc22in 49 rw ace_clk_cr0 89 rw c9 prt2ic0 0a rw dcc22ou 4a rw ace_clk_cr1 8a rw ca prt2ic1 0b rw dcc22cr1 4b rw ace_clk_cr3 8b rw cb prt3dm0 0c rw dcc23fn 4c rw 8c rw cc prt3dm1 0d rw dcc23in 4d rw ace01cr1 8d rw cd prt3ic0 0e rw dcc23ou 4e rw ace01cr2 8e rw ce prt3ic1 0f rw dcc23cr1 4f rw ase11cr0 8f rw cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 dec0_cr0 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 dec_cr3 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 93 gdi_e_ou d3 rw prt5dm0 14 rw 54 94 dec0_cr d4 rw prt5dm1 15 rw 55 dec1_cr0 95 rw dec1_cr d5 rw prt5ic0 16 rw 56 dec_cr4 96 rw dec2_cr d6 rw prt5ic1 17 rw 57 97 dec3_cr d7 rw 18 58 98 mux_cr0 d8 rw 19 59 dec2_cr0 99 rw mux_cr1 d9 rw 1a 5a dec_cr5 9a rw mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c idac_cr1 dc rw 1d 5d dec3_cr0 9d rw osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw clk_cr0 60 rw gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw clk_cr1 61 rw gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw abf_cr0 62 rw gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw amd_cr0 63 rw gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw cmp_go_en 64 rw rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw cmp_go_en1 65 rw rtc_m a5 rw adc0_tr e5 rw dbc01ou 26 rw amd_cr1 66 rw rtc_s a6 rw adc1_tr e6 rw dbc01cr1 27 rw alt_cr0 67 rw rtc_cr a7 rw idac_cr2 e7 rw dcc02fn 28 rw alt_cr1 68 rw sadc_cr0 a8 rw imo_tr e8 rw dcc02in 29 rw clk_cr2 69 rw sadc_cr1 a9 rw ilo_tr e9 rw dcc02ou 2a rw amux_cfg1 6a rw sadc_cr2 aa rw bdg_tr ea rw dcc02cr1 2b rw i2c1_cfg 6b rw sadc_cr3 ab rw eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw mux_cr5 ed rw dcc03ou 2e rw tmp_dr2 6e rw i2c1_addr ae rw ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw sadc_tscr0 71 rw rdi0syn b1 rw f1 dbc10ou 32 rw sadc_tscr1 72 rw rdi0is b2 rw f2 dbc10cr1 33 rw ace_amd_cr0 73 rw rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rdi0lt1 b4 rw f4 dbc11in 35 rw ace_amx_in 75 rw rdi0ro0 b5 rw f5 dbc11ou 36 rw ace_cmp_cr0 76 rw rdi0ro1 b6 rw f6 dbc11cr1 37 rw ace_cmp_cr1 77 rw rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw ace_cmp_gi_en 79 rw rdi1syn b9 rw f9 dcc12ou 3a rw ace_alt_cr0 7a rw rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw ace_abf_cr0 7b rw rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw ace0_cr1 7d rw rdi1ro0 bd rw idac_cr0 fd rw dcc13ou 3e rw ace0_cr2 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw ace0_cr3 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 30 of 80 table 20. cy8c28x52 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 asc10cr0 80 rw c0 prt0ie 01 rw 41 asc10cr1 81 rw c1 prt0gs 02 rw 42 asc10cr2 82 rw c2 prt0dm2 03 rw 43 asc10cr3 83 rw c3 prt1dr 04 rw 44 asd11cr0 84 rw c4 prt1ie 05 rw 45 asd11cr1 85 rw c5 prt1gs 06 rw 46 asd11cr2 86 rw c6 prt1dm2 07 rw 47 asd11cr3 87 rw c7 prt2dr 08 rw 48 asc12cr0 88 rw c8 prt2ie 09 rw 49 asc12cr1 89 rw c9 prt2gs 0a rw 4a asc12cr2 8a rw ca prt2dm2 0b rw 4b asc12cr3 8b rw cb prt3dr 0c rw 4c asd13cr0 8c rw cc prt3ie 0d rw 4d asd13cr1 8d rw cd prt3gs 0e rw 4e asd13cr2 8e rw ce prt3dm2 0f rw 4f asd13cr3 8f rw cf prt4dr 10 rw 50 asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw 51 asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw 52 asd20cr2 92 rw d2 prt4dm2 13 rw 53 asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw 54 asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw 55 asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw 56 asc21cr2 96 rw i2c0_cfg d6 rw prt5dm2 17 rw 57 asc21cr3 97 rw i2c0_scr d7 # 18 58 asd22cr0 98 rw i2c0_dr d8 rw 19 59 asd22cr1 99 rw i2c0_mscr d9 # 1a 5a asd22cr2 9a rw int_clr0 da rw 1b 5b asd22cr3 9b rw int_clr1 db rw 1c 5c asc23cr0 9c rw int_clr2 dc rw 1d 5d asc23cr1 9d rw int_clr3 dd rw 1e 5e asc23cr2 9e rw int_msk3 de rw 1f 5f asc23cr3 9f rw int_msk2 df rw dbc00dr0 20 # amx_in 60 rw dec0_dh a0 rc int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw dec0_dl a1 rc int_msk1 e1 rw dbc00dr2 22 rw clk_cr3 62 rw dec1_dh a2 rc int_vc e2 rc dbc00cr0 23 # arf_cr 63 rw dec1_dl a3 rc res_wdt e3 w dbc01dr0 24 # cmp_cr0 64 # dec2_dh a4 rc e4 dbc01dr1 25 w asy_cr 65 # dec2_dl a5 rc e5 dbc01dr2 26 rw cmp_cr1 66 rw dec3_dh a6 rc dec_cr0* e6 rw dbc01cr0 27 # 67 dec3_dl a7 rc dec_cr1* e7 rw dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcc02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbc10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbc10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbc10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbc11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbc11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbc11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbc11cr0 37 # acb01cr2 77 rw rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcc12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcc12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcc12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcc13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw dac1_d fc rw dcc13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw dac0_d fd rw dcc13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # acb03cr2 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 31 of 80 table 21. cy8c28x52 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 80 c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 ace_amd_cr1 83 rw c3 prt1dm0 04 rw 44 84 c4 prt1dm1 05 rw 45 ace_pwm_cr 85 rw c5 prt1ic0 06 rw 46 ace_adc0_cr 86 rw c6 prt1ic1 07 rw 47 ace_adc1_cr 87 rw c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 ace_clk_cr0 89 rw c9 prt2ic0 0a rw 4a ace_clk_cr1 8a rw ca prt2ic1 0b rw 4b ace_clk_cr3 8b rw cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d ace01cr1 8d rw cd prt3ic0 0e rw 4e ace01cr2 8e rw ce prt3ic1 0f rw 4f ase11cr0 8f rw cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 dec0_cr0 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 dec_cr3 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 93 gdi_e_ou d3 rw prt5dm0 14 rw 54 94 dec0_cr d4 rw prt5dm1 15 rw 55 dec1_cr0 95 rw dec1_cr d5 rw prt5ic0 16 rw 56 dec_cr4 96 rw dec2_cr d6 rw prt5ic1 17 rw 57 97 dec3_cr d7 rw 18 58 98 mux_cr0 d8 rw 19 59 dec2_cr0 99 rw mux_cr1 d9 rw 1a 5a dec_cr5 9a rw mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c idac_cr1 dc rw 1d 5d dec3_cr0 9d rw osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw clk_cr0 60 rw gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw clk_cr1 61 rw gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw abf_cr0 62 rw gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw amd_cr0 63 rw gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw cmp_go_en 64 rw rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw cmp_go_en1 65 rw rtc_m a5 rw adc0_tr e5 rw dbc01ou 26 rw amd_cr1 66 rw rtc_s a6 rw adc1_tr e6 rw dbc01cr1 27 rw alt_cr0 67 rw rtc_cr a7 rw idac_cr2 e7 rw dcc02fn 28 rw alt_cr1 68 rw a8 imo_tr e8 rw dcc02in 29 rw clk_cr2 69 rw a9 ilo_tr e9 rw dcc02ou 2a rw amux_cfg1 6a rw aa bdg_tr ea rw dcc02cr1 2b rw 6b ab eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw ac mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw mux_cr5 ed rw dcc03ou 2e rw tmp_dr2 6e rw ae ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw 71 rdi0syn b1 rw f1 dbc10ou 32 rw 72 rdi0is b2 rw f2 dbc10cr1 33 rw ace_amd_cr0 73 rw rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rdi0lt1 b4 rw f4 dbc11in 35 rw ace_amx_in 75 rw rdi0ro0 b5 rw f5 dbc11ou 36 rw ace_cmp_cr0 76 rw rdi0ro1 b6 rw f6 dbc11cr1 37 rw ace_cmp_cr1 77 rw rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw ace_cmp_gi_en 79 rw rdi1syn b9 rw f9 dcc12ou 3a rw ace_alt_cr0 7a rw rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw ace_abf_cr0 7b rw rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw ace0_cr1 7d rw rdi1ro0 bd rw idac_cr0 fd rw dcc13ou 3e rw ace0_cr2 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw ace0_cr3 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 32 of 80 electrical specifications this section presents the dc and ac electric al specifications of the cy8c28xxx psoc devi ces. for the most up to date electrical specifications, confirm that you have the most recent datasheet by going to the web at http//www.cypress.com. specifications are valid for -40 o c ? t a ? 85 c and t j ? 100 c, except where noted. sp ecifications for devices running at greater than 12 mhz are valid for -40 c ? t a ? 70 c and t j ? 82 c. figure 7. voltage versus cpu frequency 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage v al i d o p e r at i n g r e g i o n
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 33 of 80 absolute maximum ratings operating temperature table 22. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temper- ature is +25 c 25 c. extended duration storage temperatures above 65 c degrade reliability. t baketemp bake temperature - 125 see package label o c t baketime bake time see package label - 72 hours t a ambient temperature with power applied -40 ? +85 c v dd supply voltage on v dd relative to v ss -0.5 ? +6.0 v v io dc input voltage v ss - 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tri-state v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma i maio maximum current into any port pin configured as analog driver -50 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma table 23. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 c t j junction temperature -40 ? +100 c the temperature rise from ambient to junction is package specific. see thermal imped- ances on page 66. the user must limit the power consumption to comply with this requirement.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 34 of 80 dc electrical characteristics dc chip level specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 24. dc chip level specifications symbol description min typ max units notes v dd supply voltage 3.00 ? 5.25 v i dd supply current ? 8 14 ma conditions are v dd = 5.0 v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled. vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz. i dd3 supply current ? 5 9 ma conditions are v dd = 3.3 v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled. vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz. i ddp supply current when imo = 6 mhz using slimo mode=1 ? 2 3 ma conditions are v dd = 3.3 v, t a = 25 c, cpu = 0.75 mhz, sysclk doubler disabled, vc1 = 0.375 mhz, vc2 = 23.44 khz, vc3 = 0.09 khz. i sb sleep (mode) current with por, lvd, sleep timer, and wdt. [15] ? 3 10 ? a conditions are with internal slow speed oscillator, v dd = 3.3 v, ?40 c ? t a ? 55 c. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature. [15] ? 4 25 ? a conditions are with internal slow speed oscillator, v dd = 3.3 v, 55 c < t a ? 85 c. i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal. [15] ? 4 13 ? a conditions are with properly loaded, 1 ? w max, 32.768 khz crystal. v dd = 3.3 v, ?40 c ? t a ? 55 c. i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal at high temperature. [15] ? 5 26 ? a conditions are with properly loaded, 1 ? w max, 32.768 khz crystal. v dd = 3.3 v, 55 c < t a ? 85 c. i sbrtc current consumed by rtc during sleep ? 0.5 1 a extra current consumed by the rtc during sleep. this number is typical at 25 c and 5 v. v ref reference voltage (bandgap) 1.280 1.300 1.320 v trimmed for appropriate v dd . i sxres supply current with xres asserted 5 v ? 0.65 3 ma max is peak current after xres; typical value is the steady state current value. t a = 25 c. supply current with xres asserted 3.3 v - 0.4 1.5 ma note 15. standby (sleep) current includes all function s (por, lvd, wdt, sleep timer) needed for reliable system op eration. this should be compared with devices that have similar functions enabled.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 35 of 80 dc gpio specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 25. dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined i oh budget. v ol low output level ? ? 0.75 v i ol = 25 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined i ol budget. i oh high level source current 10 ? ? ma v oh = v dd ? 1.0 v, see the limita- tions of the total current in the note for v oh. i ol low level sink current 25 ? ? ma v ol = 0.75 v, see the limitations of the total current in the note for v ol. v il input low level ? ? 0.8 v v dd = 3.0 to 5.25. v ih input high level 2.1 ? ? v v dd = 3.0 to 5.25. v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 ? a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 c.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 36 of 80 dc operational amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the operational amplifiers cove red by these specifications ar e components of both the analog continuous time psoc blocks and the analog switched cap psoc bl ocks. the guaranteed specifications are measured in the analog continuous time psoc block. table 26. 5 v dc operational amplifier specifications symbol description min typ max units notes v osoact input offset voltage ct block (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? 1.6 1.3 1.2 8 8 8 mv mv mv v osoa input offset voltage sc and agnd opamps (absolute value) ? 1 6 mv applies to high and low opamp bias. tcv osoa average input offset voltage drift ? 7.0 35.0 ? v/ c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 ? a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 c. v cmoa common mode voltage range common mode voltage range (high power or high opamp bias) 0.0 ? v dd v dd ? 0.5 v v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. 0.5 ? cmrr oa common mode rejection ratio power = low power = medium power = high 60 60 60 ? ? ? ? ? ? db db db g oloa open loop gain power = low power = medium power = high 60 60 80 ? ? ? ? ? ? db db db v ohighoa high output voltage swing (internal signals) power = low power = medium power = high v dd ? 0.2 v dd ? 0.2 v dd ? 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low power = medium power = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 200 400 700 1400 2400 4600 300 600 1100 2000 3600 7700 ? a ? a ? a ? a ? a ? a psrr oa supply voltage rejection ratio 60 ? ? db v ss ? v in ? (v dd ? 2.25) or (v dd ? 1.25 v) ? v in ? v dd .
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 37 of 80 table 27. 3.3 v dc operational amplifier specifications symbol description min typ max units notes v osoact input offset voltage ct blocks (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? 1.65 1.32 ? 8 8 ? mv mv mv v osoa input offset voltage sc and agnd (absolute value) ? 1 6 mv applies to high and low opamp bias. tcv osoa average input offset voltage drift ? 7.0 35.0 ? v/ c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 ? a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c . v cmoa common mode voltage range 0.2 ? v dd ? 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. cmrr oa common mode rejection ratio power = low power = medium power = high 50 50 50 ? ? ? ? ? ? db db db g oloa open loop gain power = low power = medium power = high 60 60 80 ? ? ? ? ? ? db db db v ohighoa high output voltage swing (internal signals) power = low power = medium power = high is 5 v only v dd ? 0.2 v dd ? 0.2 v dd ? 0.2 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low power = medium power = high ? ? ? ? ? ? 0.2 0.2 0.2 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 200 400 700 1400 2400 4600 300 600 1000 2000 3600 7500 ? a ? a ? a ? a ? a ? a psrr oa supply voltage rejection ratio 50 80 ? db v ss ? v in ? (v dd ? 2.25 v) or (v dd ? 1.25 v) ? v in ? v dd .
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 38 of 80 dc type-e operational am plifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the operational amplifiers cove red by these specifications ar e components of the limited type e analog psoc blocks. dc low power comparator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v at 25 c and are for design guidance only. table 28. 5 v dc type-e operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv for 0.2 v < v in < v dd ? 1.2 v. ?2.5 20mv for v in = 0 to 0.2 v and v in > v dd ? 1.2 v. tcv osoa average input offset voltage drift ? 10 ? ? v/ c i eboa [16] input leakage current (port 0 anal og pins) ? 200 ? na gross tested to 1 ? a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 c. v cmoa common mode voltage range 0.0 ? v dd v i soa amplifier supply current ? 10 30 ? a table 29. 3.3 v dc type-e oper ational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv for 0.2 v < v in < v dd ? 1.2 v. ? 2.5 20 mv for v in = 0 to 0.2 v and v in > v dd ? 1.2 v. tcv osoa average input offset voltage drift ? 10 ? ? v/ c i eboa [16] input leakage current (port 0 analog pins) ? 200 ? na gross tested to 1 ? a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 c. v cmoa common mode voltage range 0 ? v dd v i soa amplifier supply current ? 10 30 ? a note 16. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25 c; 50 na over tem perature. use port 0 pins 1-7 for the lowest leakage of 200 na . table 30. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? v dd ? 1 v v oslpc lpc voltage offset ? 2.5 30 mv i slpc lpc supply current ? 10 40 ? a
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 39 of 80 dc analog output bu ffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 31. 5 v dc analog output buffer specifications symbol description min typ max units notes c l load capacitance ? ? 200 pf this specification applies to the external circuit that is being driven by the analog output buffer. v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 20 ? v/c v cmob common-mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? ? ? v ohighob high output voltage swing (load = 32 ? to v dd /2) power = low power = high 0.5 v dd + 1.3 0.5 v dd + 1.3 ? ? ? ? v v v olowob low output voltage swing (load = 32 ? to v dd /2) power = low power = high ? ? ? ? 0.5 v dd ? 1.3 0.5 v dd ? 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 53 64 ? db (0.5 v dd ? 1.0) ? v out ? (0.5 v dd + 0.9).
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 40 of 80 table 32. 3.3 v dc analog output buffer specifications symbol description min typ max units notes c l load capacitance ? ? 200 pf this specification applies to the external circuit that is being driven by the analog output buffer. v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 20 ? v/c v cmob common-mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? ? ? v ohighob high output voltage swing (load = 1 k ? to v dd /2) power = low power = high 0.5 v dd + 1.0 0.5 v dd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1 k ? to v dd /2) power = low power = high ? ? ? ? 0.5 v dd ? 1.0 0.5 v dd ? 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 47 64 ? db (0.5 v dd ? 1.0) ? v out ? (0.5 v dd + 0.9).
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 41 of 80 dc switch mode pump specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 8. basic switch mode pump circuit table 33. dc switch mode pump (smp) specifications symbol description min typ max units notes v pump 5 v 5 v output voltage 4.75 5.0 5.2 5 v configuration of footnote. [17] average, neglecting ripple. smp trip voltage is set to 5.0 v. v pump 3 v 3 v output voltage 3.00 3.25 3. 60 v configuration of footnote. [17] average, neglecting ripple. smp trip voltage is set to 3.25 v. i pump available output current v bat = 1.5 v, v pump = 3.25 v v bat = 1.8 v, v pump = 5.0 v 8 5 ? ? ? ? ma ma configuration of footnote. [17] smp trip voltage is set to 3.25 v. smp trip voltage is set to 5.0 v. v bat 5 v input voltage range from battery 1 .8 ? 5.0 v configuration of footnote. [17] smp trip voltage is set to 5.0 v. v bat 3 v input voltage range from battery 1 .5 ? 3.3 v configuration of footnote. [17] smp trip voltage is set to 3.25 v. v batstart minimum input voltage from battery to start pump 2.6 ? ? v configuration of footnote. [17] ? v pump_line line regulation (over v bat range) ? 5 ? %v o configuration of footnote. [17] v o is the ?v dd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 40 on page 50. ? v pump_load load regulation ? 5 ? %v o configuration of footnote. [17] v o is the ?v dd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 40 on page 50. ? v pump_ripple output voltage ripple (depends on capacitor/load) ? 100 ? mvpp configuration of footnote. [17] load is 5ma. e 3 efficiency 35 50 ? % configuration of footnote. [17] load is 5 ma. smp trip voltage is set to 3.25 v. f pump switching frequency ? 1.3 ? mhz dc pump switching duty cycle ? 50 ? % note 17. l 1 = 2 uh inductor, c 1 = 10 uf capacitor, d 1 = schottky diode. see figure 8 . battery c1 d1 + psoc tm vdd vss smp v bat v pump l 1
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 42 of 80 dc analog reference specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the guaranteed specificat ions for refhi and reflo are measured through the analog continuous time psoc blocks. the power levels for refhi and reflo refer to the analog reference control register. agnd is measured at p2[4] in agnd bypass mode. each analog continuous time psoc block adds a maximum of 10mv addi tional offset error to guarante ed agnd specifications from the local agnd buffer. reference control power can be set to medium or high unless otherwise noted. note avoid using p2[4] for digital signaling when using an analog reso urce that depends on the analog reference. some coupling of the digital signal may appear on the agnd. table 34. 5-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.214 v dd /2 + 1.279 v dd /2 + 1.341 v v agnd agnd v dd /2 v dd /2 ? 0.018 v dd /2 ? 0.004 v dd /2 + 0.01 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.328 v dd /2 ? 1.301 v dd /2 ? 1.273 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 0.228 v dd /2 + 1.284 v dd /2 + 1.344 v v agnd agnd v dd /2 v dd /2 ? 0.015 v dd /2 ? 0.002 v dd /2 + 0.011 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.329 v dd /2 ? 1.303 v dd /2 ? 1.275 v refpower = medium opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.224 v dd /2 + 1.287 v dd /2 + 1.345 v v agnd agnd v dd /2 v dd /2 ? 0.014 v dd /2 ? 0.001 v dd /2 + 0.012 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.328 v dd /2 ? 1.304 v dd /2 ? 1.275 v refpower = medium opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.226 v dd /2 + 1.288 v dd /2 + 1.346 v v agnd agnd v dd /2 v dd /2 ? 0.014 v dd /2 ? 0.001 v dd /2 + 0.012 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.328 v dd /2 ? 1.304 v dd /2 ? 1.276 v note 18. agnd tolerance includes the offsets of the local buffer in the psoc block.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 43 of 80 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.055 p2[4] + p2[6] ? 0.019 p2[4] + p2[6] + 0.019 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[ 6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.030 p2[4] ? p2[6] + 0.005 p2[4] ? p2[6] + 0.035 v refpower = high opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.05 p2[4] + p2[6] ? 0.015 p2[4] + p2[6] + 0.021 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[ 6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.033 p2[4] ? p2[6] + 0.001 p2[4] ? p2[6] + 0.031 v refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.048 p2[4] + p2[6] ? 0.013 p2[4] + p2[6] + 0.022 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[ 6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.034 p2[4] ? p2[6] ? 0.001 p2[4] ? p2[6] + 0.031 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.047 p2[4] + p2[6] ? 0.012 p2[4] + p2[6] + 0.023 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[ 6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.036 p2[4] ? p2[6] ? 0.002 p2[4] ? p2[6] + 0.030 v 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.028 v dd ? 0.010 v dd v v agnd agnd v dd /2 v dd /2 ? 0.014 v dd /2 ? 0.002 v dd /2 + 0.012 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.008 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.021 v dd ? 0.007 v dd v v agnd agnd v dd /2 v dd /2 ? 0.014 v dd /2 ? 0.001 v dd /2 + 0.012 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.005 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.019 v dd ? 0.006 v dd v v agnd agnd v dd /2 v dd /2 ? 0.014 v dd /2 ? 0.001 v dd /2 + 0.012 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.004 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.017 v dd ? 0.005 v dd v v agnd agnd v dd /2 v dd /2 ? 0.014 v dd /2 ? 0.001 v dd /2 + 0.013 v v reflo ref low v ss v ss v ss + 0.001 v ss + 0.003 v table 34. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 44 of 80 0b011 refpower = high opamp bias = high v refhi ref high 3 bandgap 3.736 3.887 4.030 v v agnd agnd 2 bandgap 2.525 2.598 2.667 v v reflo ref low bandgap 1.265 1.302 1.335 v refpower = high opamp bias = low v refhi ref high 3 bandgap 3.747 3.894 4.034 v v agnd agnd 2 bandgap 2.528 2.601 2.668 v v reflo ref low bandgap 1.264 1.302 1.335 v refpower = medium opamp bias = high v refhi ref high 3 bandgap 3.749 3.897 4.035 v v agnd agnd 2 bandgap 2.529 2.602 2.668 v v reflo ref low bandgap 1.264 1.302 1.335 v refpower = medium opamp bias = low v refhi ref high 3 bandgap 3.751 3.899 4.037 v v agnd agnd 2 bandgap 2.530 2.603 2.669 v v reflo ref low bandgap 1.264 1.302 1.335 v 0b100 refpower = high opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.483 ? p2[6] 2.578 ? p2[6] 2.669 ? p2[6] v v agnd agnd 2 bandgap 2.525 2.598 2.666 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.512 ? p2[6] 2.602 ? p2[6] 2.684 ? p2[6] v refpower = high opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.495 ? p2[6] 2.586 ? p2[6] 2.673 ? p2[6] v v agnd agnd 2 bandgap 2.528 2.601 2.668 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.510 ? p2[6] 2.602 ? p2[6] 2.685 ? p2[6] v refpower = medium opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.498 ? p2[6] 2.589 ? p2[6] 2.674 ? p2[6] v v agnd agnd 2 bandgap 2.529 2.601 2.668 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.509 ? p2[6] 2.601 ? p2[6] 2.685 ? p2[6] v refpower = medium opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.500 ? p2[6] 2.591 ? p2[6] 2.675 ? p2[6] v v agnd agnd 2 bandgap 2.530 2.603 2.669 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.508 ? p2[6] 2.601 ? p2[6] 2.686 ? p2[6] v table 34. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 45 of 80 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.218 p2[4] + 1.283 p2[4] + 1.344 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.329 p2[4] ? 1.297 p2[4] ? 1.265 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.225 p2[4] + 1.287 p2[4] + 1.346 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.330 p2[4] ? 1.301 p2[4] ? 1.271 v refpower = medium opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.226 p2[4] + 1.288 p2[4] + 1.346 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.330 p2[4] ? 1.302 p2[4] ? 1.272 v refpower = medium opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.227 p2[4] + 1.289 p2[4] + 1.347 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.331 p2[4] ? 1.303 p2[4] ? 1.273 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.506 2.597 2.674 v v agnd agnd bandgap 1.263 1.302 1.336 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.014 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.508 2.595 2.675 v v agnd agnd bandgap 1.263 1.302 1.336 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.008 v refpower = medium opamp bias = high v refhi ref high 2 bandgap 2.508 2.595 2.676 v v agnd agnd bandgap 1.263 1.302 1.336 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.005 v refpower = medium opamp bias = low v refhi ref high 2 bandgap 2.508 2.596 2.677 v v agnd agnd bandgap 1.263 1.302 1.336 v v reflo ref low v ss v ss v ss + 0.001 v ss + 0.003 v table 34. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 46 of 80 0b111 refpower = high opamp bias = high v refhi ref high 3.2 bandgap 4.056 4.155 4.222 v v agnd agnd 1.6 bandgap 2.012 2.083 2.168 v v reflo ref low v ss v ss v ss + 0.01 v ss + 0.035 v refpower = high opamp bias = low v refhi ref high 3.2 bandgap 4.061 4.153 4.223 v v agnd agnd 1.6 bandgap 2.023 2.082 2.145 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.022 v refpower = medium opamp bias = high v refhi ref high 3.2 bandgap 4.063 4.154 4.224 v v agnd agnd 1.6 bandgap 2.020 2.083 2.152 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.024 v refpower = medium opamp bias = low v refhi ref high 3.2 bandgap 4.061 4.154 4.225 v v agnd agnd 1.6 bandgap 2.026 2.081 2.140 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.017 v table 35. 3.3-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.223 v dd /2 + 1.283 v dd /2 + 1.343 v v agnd agnd v dd /2 v dd /2 ? 0.013 v dd /2 ? 0.003 v dd /2 + 0.005 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.322 v dd /2 ? 1.297 v dd /2 ? 1.270 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.228 v dd /2 + 1.288 v dd /2 + 1.345 v v agnd agnd v dd /2 v dd /2 ? 0.008 v dd /2 ? 0.002 v dd /2 + 0.005 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.322 v dd /2 ? 1.298 v dd /2 ? 1.271 v refpower = medium opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.232 v dd /2 + 1.290 v dd /2 + 1.346 v v agnd agnd v dd /2 v dd /2 ? 0.008 v dd /2 ? 0.001 v dd /2 + 0.006 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.322 v dd /2 ? 1.299 v dd /2 ? 1.272 v refpower = medium opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.233 v dd /2 + 1.291 v dd /2 + 1.347 v v agnd agnd v dd /2 v dd /2 ? 0.006 v dd /2 v dd /2 + 0.006 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.322 v dd /2 ? 1.299 v dd /2 ? 1.272 v table 34. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 47 of 80 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.045 p2[4] + p2[6] ? 0.017 p2[4] + p2[6] + 0.016 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.019 p2[4] ? p2[6] + 0.004 p2[4] ? p2[6] + 0.023 v refpower = high opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.036 p2[4] + p2[6] ? 0.012 p2[4] + p2[6] + 0.013 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.021 p2[4] ? p2[6] ? 0.001 p2[4] ? p2[6] + 0.021 v refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.034 p2[4] + p2[6] ? 0.011 p2[4] + p2[6] + 0.013 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.023 p2[4] ? p2[6] ? 0.002 p2[4] ? p2[6] + 0.016 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.033 p2[4] + p2[6] ? 0.009 p2[4] + p2[6] + 0.014 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.024 p2[4] ? p2[6] ? 0.003 p2[4] ? p2[6] + 0.020 v 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.042 v dd ? 0.008 v dd v v agnd agnd v dd /2 v dd /2 ? 0.035 v dd /2 ? 0.001 v dd /2 + 0.031 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.0165 v v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.035 v dd ? 0.005 v dd v v agnd agnd v dd /2 v dd /2 ? 0.031 v dd /2 ? 0.001 v dd /2 + 0.028 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.012 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.044 v dd ? 0.005 v dd v v agnd agnd v dd /2 v dd /2 ? 0.052 v dd /2 v dd /2 + 0.046 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.014 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.036 v dd ? 0.004 v dd v v agnd agnd v dd /2 v dd /2 ? 0.032 v dd /2 v dd /2 + 0.029 v v reflo ref low v ss v ss v ss + 0.001 v ss + 0.012 v 0b011 all power settings. not allowed for 3.3 v. ?? ? ? ? ? ? 0b100 all power settings. not allowed for 3.3 v. ?? ? ? ? ? ? table 35. 3.3-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 48 of 80 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.226 p2[4] + 1.286 p2[4] + 1.343 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.323 p2[4] ? 1.293 p2[4] ?1.262 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.232 p2[4] + 1.29 p2[4] + 1.344 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.324 p2[4] ? 1.296 p2[4] ? 1.267 v refpower = medium opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.233 p2[4] + 1.291 p2[4] + 1.345 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.324 p2[4] ? 1.298 p2[4] ? 1.269 v refpower = medium opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.234 p2[4] + 1.292 p2[4] +1.345 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.324 p2[4] ? 1.299 p2[4] ? 1.270 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.504 2.595 2.672 v v agnd agnd bandgap 1.262 1.301 1.336 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.013 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.506 2.593 2.674 v v agnd agnd bandgap 1.262 1.301 1.336 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.008 v refpower = medium opamp bias = high v refhi ref high 2 bandgap 2.506 2.594 2.675 v v agnd agnd bandgap 1.262 1.301 1.335 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.007 v refpower = medium opamp bias = low v refhi ref high 2 bandgap 2.507 2.595 2.675 v v agnd agnd bandgap 1.262 1.301 1.335 v v reflo ref low v ss v ss v ss + 0.001 v ss + 0.005 v 0b111 all power settings. not allowed for 3.3 v. ?? ? ? ? ? ? table 35. 3.3-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units table 36. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.24 ? k ? c sc capacitor unit value (switch cap) ? 80 ? ff
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 49 of 80 dc analog mux bus specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc sar10 adc specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 37. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 ? v dd ? 3.0 v r vss resistance of initialization switch to v ss ? ? 800 ? table 38. dc sar10 adc specifications symbol description min typ max units notes inl sar10 integral nonlinearity for vref ?? 3 v ?2.5 ? 2.5 lsb 10-bit resolution integral nonlinearity for vref < 3 v ?5 ? 5 lsb 10-bit resolution dnl sar10 differential nonlinearity for vref ?? 3 v ?1.5 ? 1.5 lsb 10-bit resolution differential nonlinearity for vref > 3 v ?4 ? 4 lsb 10-bit resolution i sar10 active current consumption 0.08 0.5 0.497 ma i vrefsar10 input current into p2[5] when configured as the sar10 adc's vref input. ? ? 0.5 ma the internal voltage reference buffer is disabled in this configuration. v vrefsar10 input reference voltage at p2[5] when configured as the sar10 adc's external voltage reference. 2.7 ? v dd ? 0.3 v v when vref is buffered inside the sar10 adc, the voltage level at p2[5] (when configured as the external reference voltage) must always be at least 300 mv less than the chip supply voltage level on the v dd pin. (v vrefsar10 < (v dd ? 300 mv)). v ossar10 offset voltage 5 7.7 10 mv sar imp sar input impedence ? 1.64 ? m ? frequency dependant = 1/ fs c. 142.9 khz (maximum) and cin = 4.28 pf (typical) table 39. dc idac specifications symbol description min typ max units notes idac_dnl differential nonlinearity ?5.0 2.0 5.0 lsb valid for all 3 current ranges idac_inl integral nonlinearity ?5.0 2.0 5.0 lsb valid for all 3 current ranges idac_gain gain per bit ? range 1 (91 a) 283 357 447 na measured at full scale gain per bit ? range 2 (318 a) 985 1250 1532 na gain per bit ? range 3 (637 a) 1959 2500 3056 na idacoffset offset at code 0 vs lsb ideal ? range 1 (91 a) 2.0% 20% % measured as a % of lsb (current @ code 0)/(lsb ideal current) offset at code 0 vs lsb ideal ? range 2 (318 a) 1.0% 10% % offset at code 0 vs lsb ideal ? range 3 (637 a) 1.0% 10% %
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 50 of 80 dc por and lvd specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. note the bits porlev and vm in the table below refer to bits in the vlt_cr register. see the psoc technical reference manual for cy8c28xxx psoc devices, for more information on the vlt_cr register. table 40. dc por and lvd specifications symbol description min typ max units notes v ppor0r v ppor1r v ppor2r v dd value for ppor trip (positive ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 2.91 4.39 4.55 2.985 4.49 4.65 v v v v dd must be greater than or equal to 2.5 v during startup, reset from the xres pin, or reset from watchdog. v ppor0 v ppor1 v ppor2 v dd value for ppor trip (negative ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 2.82 4.39 4.55 2.90 4.49 4.64 v v v v dd must be greater than or equal to 2.5 v during startup, reset from the xres pin, or reset from watchdog. v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 92 0 0 ? ? ? mv mv mv v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.83 2.93 3.04 3.90 4.38 4.54 4.62 4.71 2.91 3.01 3.12 3.99 4.47 4.63 4.71 4.80 3.00 [19] 3.10 3.21 4.09 4.58 4.74 [20] 4.83 4.92 v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 v dd value for pump trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.93 3.00 3.16 4.09 4.53 4.61 4.70 4.88 3.01 3.08 3.24 4.17 4.62 4.71 4.80 4.98 3.10 3.17 3.33 4.28 4.74 4.82 4.91 5.10 v v v v v v v v notes 19. always greater than 50 mv above ppor (porlev = 00) for falling supply. 20. always greater than 50 mv above ppor (porlev = 10) for falling supply.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 51 of 80 dc programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 41. dc programming specifications symbol description min typ max units notes v dd p v dd for programming and erase 4.5 5 5.5 v this specification applies to the functional requirements of external programmer tools. v dd lv low v dd for verify 3 3.1 3.2 v this specification applies to the functional requirements of external programmer tools. v dd hv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools. v dd iwrite supply voltage for flash write operation 3 ? 5.25 v this specification applies to this device when it is executing internal flash writes. i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.21 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) 50,000 [21] ? ? ? erase/write cycles per block. flash ent flash endurance (total) [22] 1,800,000 ? ? ? erase/write cycles. must be programmed and read at the same voltage to meet this. flash dr flash data retention 10 ? ? years notes 21. the 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. volta ge ranges are 3.0 v to 3.6 v and 4.75 v to 5.25 v. 22. a maximum of 36 50,000 block endurance cycles is allowed. this may be balanced between operations on 36 x1 blocks of 50,000 maximum cycles each , 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x5 0,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 52 of 80 dc i 2 c specifications ta b l e 4 2 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. ac electrical characteristics ac chip-level specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 42. dc i 2 c specifications [23] symbol description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 3.0 v ?? v dd ?? 3.6 v ? ? 0.25 v dd v 4.75 v ?? v dd ?? 5.25 v v ihi2c input high level 0.7 v dd ? ? v 3.0 v ?? v dd ?? 5.25 v note 23. all gpios meet the dc gpio v il and v ih specifications found in the dc gpio specifications sections. the i 2 c gpio pins also meet the above specs. table 43. ac chip-level specifications symbol description min typ max units notes f imo internal main oscillator frequency 23.4 24 24.6 [24] mhz trimmed. utilizing factory trim values. slimo mode = 0. f imo6 internal main oscillator frequency for 6mhz 5.5 6 6.5 [24] mhz trimmed for 5 v or 3.3 v operation using factory trim values. slimo mode = 1. f cpu1 cpu frequency (5 v nominal) 0.091 24 24.6 [24] mhz trimmed. utilizing factory trim values. slimo mode = 0. f cpu2 cpu frequency (3.3 v nominal) 0.091 12 12.3 [25] mhz trimmed. utilizing factory trim values. slimo mode = 0. f blk5 digital psoc block frequency 0 ? 49.2 [24, 26] mhz 4.75 v< v dd <5.25 v f blk33 digital psoc block frequency 0 24 24.6 [26] mhz 3.0 v< v dd <3.6 v f 32k1 internal low speed oscillator frequency 15 32 64 khz trimmed. utilizing factory trim values. f 32k2 external crystal oscillator ? 32.768 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. f 32k_u internal low speed oscillator untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on timing this. f pll pll frequency ? 23.986 ? mhz multiple (x732) of crystal frequency. t pllslew pll lock time 0.5 ? 10 ms t pllslewslo w pll lock time for low gain setting 0.5 ? 50 ms t os external crystal oscillator startup to 1% ? 1700 2620 ms t osacc external crystal oscillator startup to 100 ppm ? 2800 3800 ms the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct operation assumes a properly loaded 1 w maximum drive level 32.768 khz crystal. 3.0 v ? v dd ? 5.5 v, ?40 c ? t a ? 85 c . t xrst external reset pulse width 10 ? ? ? s dc24m 24 mhz duty cycle 40 50 60 %
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 53 of 80 figure 9. pll lock timing diagram figure 10. pll lock for low gain setting timing diagram dc ilo internal low speed oscillator duty cycle 20 50 80 % fout48m 48 mhz output frequency 46.8 48.0 49.2 [24,25] mhz trimmed. utilizing factory trim values. f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz sr powerup supply ramp time 0 ? ? ? s t powerup time for por release to code execution ? 16 100 ms t jit_imo [27] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 1300 ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 1300 ps n = 32 24 mhz imo period jitter (rms) ? 200 800 ps t jit_pll [27] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 1100 ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 400 2800 ps n = 32 24 mhz imo period jitter (rms) ? 200 1400 ps table 43. ac chip-level specifications (continued) symbol description min typ max units notes notes 24. 4.75 v < v dd < 5.25 v. 25. 3.0 v < v dd < 3.6 v. see application note adjusting psoc ? trims for 3.3 v and 2.7 v operation ? an2012 for information on trimming for operation at 3.3 v. 26. see the individual user module datasheets for information on maximum frequencies for user modules. 27. refer to cypress jitter specifications application note, understanding datasheet jitter specificati ons for cypress timing products ? an5054 for more information. 24 mhz f pll pll enable t pllslew pll gain 0 24 mhz f pll pll enable t pllslewlow pll gain 1
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 54 of 80 figure 11. external crystal o scillator startup timing diagram ac gpio specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 12. gpio timing diagram ac operational amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the operational amplifiers cove red by these specifications ar e components of both the analog continuous time psoc blocks and the analog switched cap psoc bl ocks. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3 v. 32 khz f 32k2 32k select t os table 44. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12.3 mhz normal strong mode t risef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns v dd = 4.5 to 5.25 v, 10% ? 90% t fallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns v dd = 4.5 to 5.25 v, 10% ? 90% t rises rise time, slow strong mode, cload = 50 pf 10 27 ? ns v dd = 3 to 5.25 v, 10% ? 90% t falls fall time, slow strong mode, cload = 50 pf 10 22 ? ns v dd = 3 to 5.25 v, 10% ? 90% tfallf tfalls tris ef trises 90% 10% gpio pin output voltage table 45. 5 v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time from 80% of ? v to 0.1% of ? v (active probe loading, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 ? s ? s ? s t soa falling settling time from 20% of ? v to 0.1% of ? v (active probe loading, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 ? s ? s ? s
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 55 of 80 sr roa rising slew rate (20% to 80%)(active probe loading, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ ? s v/ ? s v/ ? s sr foa falling slew rate (80% to 20%)(active probe loading, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ ? s v/ ? s v/ ? s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz power = medium, opamp bias = high ? 100 ? nv/rt-hz table 45. 5 v ac operational amplifier specifications (continued) symbol description min typ max units notes table 46. 3.3 v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time from 80% of ? v to 0.1% of ? v (active probe loading, unity gain) power = low, opamp bias = low power = low, opamp bias = high ? ? ? ? 3.92 0.72 ? s ? s t soa falling settling time from 20% of ? v to 0.1% of ? v (active probe loading, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 ? s ? s sr roa rising slew rate (20% to 80%)(active probe loading, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/ ? s v/ ? s sr foa falling slew rate (80% to 20%)(active probe loading, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/ ? s v/ ? s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz power = medium, opamp bias = high ? 100 ? nv/rt-hz
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 56 of 80 when bypassed by a capacitor on p2[4], the noise of the analog gr ound signal distributed to each block is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacit or. figure 13. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. at high frequencies, increased power level reduces the noise spectrum level. figure 14. typical opamp noise vnagnd emerald = 2*vbg -150 -140 -130 -120 -110 -100 -90 0.001 0.01 0.1 1 10 100 e0 . 0 e0 . 0 1 e0 . 1 e1 . 0 e1 0 . 0 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_bl pl_ bl
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 57 of 80 ac type-e operational amplifier specifications ta b l e 4 7 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively . typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guid ance only. the operational amplif iers covered by these specificat ions are components of the limited type e analog psoc blocks. ac low power comparator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v at 25 c and are for design guidance only. table 47. ac type-e operational amplifier specifications symbol description min typ max units notes t comp comparator mode response time ? 75 100 ns 50 mv overdrive. table 48. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 ? s ? 50 mv overdrive.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 58 of 80 ac digital block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 49. ac digital block specifications function description min typ max units notes all functions block input clock frequency v dd ? 4.75 v ? ? 49 mhz v dd < 4.75 v ? ? 25 mhz timer input clock frequency no capture, v dd ? 4.75 v ? ? 49 mhz no capture, v dd < 4.75 v ? ? 25 mhz with capture ? ? 25 mhz capture pulse width 50 [28] ??ns counter input clock frequency no enable input, v dd ? 4.75 v ? ? 49 mhz no enable input, v dd < 4.75 v ? ? 25 mhz with enable input ? ? 25 mhz enable input pulse width 50 [28] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [28] ??ns disable mode 50 [28] ??ns input clock frequency v dd ? 4.75 v ? ? 49 mhz v dd < 4.75 v ? ? 25 mhz crcprs (prs mode) input clock frequency v dd ? 4.75 v ? ? 49 mhz v dd < 4.75 v ? ? 25 mhz crcprs (crc mode) input clock frequency ? ? 25 mhz spim input clock frequency ? ? 8.2 mh z the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.1 mhz the input clock is the spi sclk in spis mode. width of ss_negated between transmissions 50[13] ? ? ns tranmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd ? 4.75 v, 2 stop bits ? ? 49 mhz v dd ? 4.75 v, 1 stop bit ? ? 25 mhz v dd < 4.75 v ? ? 25 mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd ? 4.75 v, 2 stop bits ? ? 49 mhz v dd ? 4.75 v, 1 stop bit ? ? 25 mhz v dd < 4.75 v ? ? 25 mhz note 28. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period).
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 59 of 80 ac analog output buffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 50. 5 v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.5 2.9 ? s ? s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.3 2.3 ? s ? s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ ? s v/ ? s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ ? s v/ ? s bw ob small signal bandwidth, 20mv pp , 3db bw, 100 pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1 v pp , 3db bw, 100 pf load power = low power = high 300 300 ? ? ? ? khz khz table 51. 3.3 v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 3.8 3.8 ? s ? s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 3.2 2.9 ? s ? s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ ? s v/ ? s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ ? s v/ ? s bw ob small signal bandwidth, 20mv pp , 3db bw, 100 pf load power = low power = high 0.64 0.64 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1 v pp , 3db bw, 100 pf load power = low power = high 200 200 ? ? ? ? khz khz
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 60 of 80 ac sar10 adc specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. ac external clock specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. ac programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 52. ac sar10 adc specifications symbol description min typ max units notes f insar10 input clock frequency for sar10 adc ? ? 2.0 mhz f ssar10 sample rate for sar10 adc sar10 adc resolution = 10 bits ? ? 142.9 ksps for 10-bit resolution, the sample rate is the adc's input clock divided by 14. table 53. 5 v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ? 24.6 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power-up imo to switch 150 ? ? ? s table 54. 3.3 v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 [29] 0.093 ?12.3mhz f oscext frequency with cpu clock divide by 2 or greater [30] 0.186 ?24.6mhz ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power-up imo to switch 150 ? ? ? s table 55. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 40 ? ms t dsclk data out delay from falling edge of sclk ? ? 55 ns v dd ? 3.6
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 61 of 80 ac i 2 c specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 15. definition for timing for fast/standard mode on the i 2 c bus t dsclk3 data out delay from falling edge of sclk ? ? 75 ns 3.0 ? v dd ? 3.6 t eraseall flash erase time (bulk) ? 40 ? ms erase all blocks and protection fields at once. t program_hot flash block erase + flash block write time ? ? 100 [31] ms 0 c ? tj ? 100 c t program_cold flash block erase + flash block write time ? ? 200 [31] ms ?40 c ? tj ? 0 c table 55. ac programming specifications symbol description min typ max units notes notes 29. maximum cpu frequency is 12 mhz at 3.3 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 30. if the frequency of the external clock is greater than 12 mhz, th e cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensu res that the fifty percent duty cycle requirement is met . 31. for the full industrial range, the user must employ a temperat ure sensor user module (flashtemp) and feed the result to the temperature argument before writing. refer to the flash apis application note, an2015 at http://ww.cypress.com under application notes for more information. 32. a fast-mode i2c-bus device can be used in a st andard-mode i2c-bus system, but the requirement t sudati2c ? 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal . if such device does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t sudati2c = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. table 56. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? ? s t highi2c high period of the scl clock 4.0 ?0.6 ? ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? ? s t hddati2c data hold time 0 ?0 ? ? s t sudati2c data setup time 250 ?100 [32] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 62 of 80 packaging information this section illustrates the packaging spec ifications for the cy8c28xxx psoc devices , along with the the rmal impedances for eac h package and the typical package capacitance on crystal pins. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools' dimensions, refer to the emulator pod dimension drawings at http://www.cypress.com. . packaging dimensions figure 16. 20-pin ssop (210 mils) package outline, 51-85077 51-85077 *e
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 63 of 80 figure 17. 28-pin ssop (210 mils) package outline, 51-85079 figure 18. 44-pin tqfp (10 10 1.4 mm) package outline, 51-85064 51-85079 *e 51-85064 *e
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 64 of 80 figure 19. 48-pin qfn (7 7 1. 0 mm) package outline, 001-45616 important note for information on the preferred dimensions for mounting qfn packages, see the following application note, ?application notes for surface mount assembly of amkor's microleadframe (mlf) packages" available at http://www.amkor.com. 001-45616 *d
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 65 of 80 figure 20. 56-pin ssop (300 mils) package outline, 51-85062 51-85062 *f
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 66 of 80 thermal impedances capacitance on crystal pins solder reflow specifications ta b l e 5 9 shows the solder reflow temperature limits that must not be exceeded. table 57. thermal impedances per package package typical ? ja [33] 20-ssop 80.8 c/w 28-ssop 45.4 c/w 44-tqfp 24.0 c/w 48-qfn [34] 16.7 c/w 56-ssop 67.5 c/w table 58. typical package capacitance on crystal pins package package capacitance 20-ssop pin9 = 0.0056 pf pin11 = 0.006048 pf 28-ssop pin13 = 0.006796 pf pin15 = 0.006755 pf 44-tqfp pin16 = 0.009428 pf pin18 = 0.008635 pf 48-qfn pin17 = 0.008493 pf pin19 = 0.008742 pf 56-ssop pin27 = 0.007916 pf pin31 = 0.007132 pf table 59. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 20-ssop 260 c 30 seconds 28-ssop 260 c 30 seconds 44-tqfp 260 c 30 seconds 48-qfn 260 c 30 seconds 56-ssop 260 c 30 seconds notes 33. t j = t a + power ? ja 34. to achieve the thermal impedance specified for the qfn package, refer to application notes for surface mount assembly of amk or's microleadframe (mlf) packages available at http://www.amkor.com for pcb requirements . 35. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 c with sn-pb or 245 5 c with sn-ag-cu paste. refer to the solder manufacturer specifications.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 67 of 80 development tool selection this section presents the development t ools available for all current psoc device families including the cy8c28xxx family. software psoc designer at the core of the psoc development software suite is psoc designer. utilized by thousands of psoc developers, this robust software has been facilitating psoc designs for over half a decade. psoc designer is available free of charge at http://www.cypress.com . psoc programmer flexible enough to be used on the bench in development, yet suitable for factory progra mming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice- cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com. development kits all development kits can be purchased from the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specif ic memory locations. advanced emulation features are support ed in psoc designer. the kit includes: psoc designer software cd ice-cube in-circuit emulator pod kit for cy8c29x66 psoc family cat-5 adapter mini-eval programming board 110 ~ 240 v power supply, euro-plug adapter issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466-24pxi 28-pdip chip samples evaluation tools all evaluation tools can be purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping prog rammer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiomete r, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 68 of 80 device programmers all device programmers can be purchased from the cypress online store. cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a producti on-programming environment. note the cy3207issp programmer needs the psoc issp software. it is not compat ible with the psoc programmer software. the latest psoc issp software for this kit can be downloaded from http://www.cypress.com . the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, euro-plug adapter usb 2.0 cable accessories (emula tion and programming) table 60. emulation and programming accessories part # pin package pod kit [36] foot kit [37] adapter [38] cy8c28243-24pvxi 20-ssop cy3250-28xxx cy3250-20ssop-fk adapters can be found at http://www.emulation.com. cy8c28403-24pvxi cy8c28413-24pvxi cy8c28433-24pvxi cy8c28445-24pvxi cy8c28452-24pvxi 28-ssop cy3250-28xxx cy3250-28ssop-fk cy8c28513-24axi CY8C28533-24axi cy8c28545-24axi 44-tqfp cy3250-28xxx cy3250-44tqfp-fk cy8c28623-24ltxi cy8c28643-24ltxi cy8c28645-24ltxi 48-qfn cy3250-28xxxq fn cy3250-48qfn-fk notes 36. pod kit contains an emulation pod, a flex-cable (co nnects the pod to the ice), two feet, and device samples. 37. foot kit includes surface mount feet that can be soldered to the target pcb. 38. programming adapter converts non-dip package to dip footprin t. specific details and ordering information for each of the ada pters can be found at http://www.emulation.com .
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 69 of 80 ordering information the following table lists the cy 8c28xxx psoc devices key package features and ordering codes. note for die sales information, contact a local cypress sales office or field applications engineer (fae). package ordering code temperature range capsense digital blocks regular analog blocks limited analog blocks hw i 2 c decimators 10-bit sar adc digital i/o pins analog inputs analog outputs flash (kbytes) ram (kbytes) xres pin 28-pin (210-mil) ssop cy8c 28403-24pvxi ?40 c to 85 c n 12 0 0 2 0 y 24 8 0 16 1 y 28-pin (210-mil) ssop (tape and reel) cy8c28403-24pvxit ?40 c to 85 c n 12 0 0 2 0 y 24 8 0 16 1 y 28-pin (210-mil) ssop cy8c 28413-24pvxi ?40 c to 85 c y 12 0 4 1 2 y 24 24 0 16 1 y 28-pin (210-mil) ssop (tape and reel) cy8c28413-24pvxit ?40 c to 85 c y 12 0 4 1 2 y 24 24 0 16 1 y 44-pin tqfp cy8c28513-24axi ?40 c to 85 c y 12 0 4 1 2 y 40 40 0 16 1 y 44-pin tqfp (tape and reel) cy8c28513-24axit ?40 c to 85 c y 12 0 4 1 2 y 40 40 0 16 1 y 48-pin sawn qfn cy8c28623-24ltxi ?40 c to 85 c n 12 6 0 2 2 n 44 10 2 16 1 y 48-pin sawn qfn (tape and reel) cy8c28623-24ltxit ?40 c to 85 c n 12 6 0 2 2 n 44 10 2 16 1 y 28-pin (210-mil) ssop cy8c 28433-24pvxi ?40 c to 85 c y 12 6 4 1 4 y 24 24 2 16 1 y 28-pin (210-mil) ssop (tape and reel) cy8c28433-24pvxit ?40 c to 85 c y 12 6 4 1 4 y 24 24 2 16 1 y 44-pin tqfp CY8C28533-24axi ?40 c to 85 c y 12 6 4 1 4 y 40 40 2 16 1 y 44-pin tqfp (tape and reel) CY8C28533-24axit ?40 c to 85 c y 12 6 4 1 4 y 40 40 2 16 1 y 20-pin (210-mil) ssop cy8c 28243-24pvxi ?40 c to 85 c n 12 12 0 2 4 y 16 16 4 16 1 y 20-pin (210-mil) ssop (tape and reel) cy8c28243-24pvxit ?40 c to 85 c n 12 12 0 2 4 y 16 16 4 16 1 y 48-pin sawn qfn cy8c28643-24ltxi ?40 c to 85 c n 12 12 0 2 4 y 44 44 4 16 1 y 48-pin sawn qfn (tape and reel) cy8c28643-24ltxit ?40 c to 85 c n 12 12 0 2 4 y 44 44 4 16 1 y 28-pin (210-mil) ssop cy8c 28445-24pvxi ?40 c to 85 c y 12 12 4 2 4 y 24 24 4 16 1 y 28-pin (210-mil) ssop (tape and reel) cy8c28445-24pvxit ?40 c to 85 c y 12 12 4 2 4 y 24 24 4 16 1 y 44-pin tqfp cy8c28545-24axi ?40 c to 85 c y 12 12 4 2 4 y 40 40 4 16 1 y 44-pin tqfp (tape and reel) cy8c28545-24axit ?40 c to 85 c y 12 12 4 2 4 y 40 40 4 16 1 y 48-pin sawn qfn cy8c28645-24ltxi ?40 c to 85 c y 12 12 4 2 4 y 44 44 4 16 1 y 48-pin sawn qfn (tape and reel) cy8c28645-24ltxit ?40 c to 85 c y 12 12 4 2 4 y 44 44 4 16 1 y 28-pin (210-mil) ssop cy8c 28452-24pvxi ?40 c to 85 c y 8 12 4 1 4 n 24 24 4 16 1 y 28-pin (210-mil) ssop (tape and reel) cy8c28452-24pvxit ?40 c to 85 c y 8 12 4 1 4 n 24 24 4 16 1 y 56-pin ssop ocd cy8c28000-24pvxi ?40 c to 85 c y 12 12 4 2 4 y 44 44 4 16 1 y
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 70 of 80 ordering code definitions cy 8 c 28 xxx - sp xxxx package type: thermal rating: pvx = ssop pb-free c = commercial ltx = qfn pb-free i = industrial ax = tqfp pb-free e = extended cpu speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 71 of 80 acronyms acronyms used ta b l e 6 1 lists the acronyms that are used in this document. reference documents cy8cplc20, cy8cled16p01, cy8c29x66, cy8c27x43, cy8c24 x94, cy8c24x23, cy8c24x23a, cy8c22x13, cy8c21x34, cy8c21x23, cy7c64215, cy7c603xx, cy8cnp1xx, and cywu sb6953 psoc? programmable system-on-chip technical reference manual (trm) (001-14463) design aids ? reading and writing psoc ? flash ? an2015 (001-40459) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . table 61. acronyms used in this datasheet acronym description acronym description ac alternating current mips million instructions per second adc analog-to-digital converter ocd on-chip debug api application programming interface pcb printed circuit board cmos complementary metal oxide semiconductor pdip plastic dual-in-line package cpu central processing unit pga programmable gain amplifier crc cyclic redundancy check pll phase-locked loop ct continuous time por power on reset dac digital-to-analog converter ppor precision power on reset dc direct current prs pseudo-random sequence dtmf dual-tone multi-frequency pso c? programmable system-on-chip eco external crystal oscillator pwm pulse width modulator eeprom electrically erasable programmable read-only memory qfn quad flat no leads gpio general purpose i/o rtc real time clock ice in-circuit emulator sar successive approximation ide integrated development environment sc switched capacitor ilo internal low speed oscillator slimo slow imo imo internal main oscillator smp switch mode pump i/o input/output soic small-outline integrated circuit irda infrared data association spi tm serial peripheral interface issp in-system serial programming sram static random access memory lcd liquid crystal display srom supervisory read only memory led light-emitting diode ssop shrink small-outline package lpc low power comparator uart universal asynchronous receiver / transmitter lvd low voltage detect usb universal serial bus mac multiply-accumulate wdt watchdog timer mcu microcontroller unit xres external reset
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 72 of 80 document conventions units of measure ta b l e 6 2 lists the unit sof measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 62. units of measure symbol unit of measure symbol unit of measure kb 1024 bytes s microsecond db decibels ms millisecond c degree celsius ns nanosecond ff femto farad ps picosecond pf picofarad v microvolts khz kilohertz mv millivolts mhz megahertz mvpp millivolts peak-to-peak rt-hz root hertz nv nanovolts k ? kilohm v volts ? ohm w microwatts a microampere w watt ma milliampere mm millimeter na nanoampere ppm parts per million pa pikoampere % percent mh millihenry glossary active high 5. a logic signal having its asserted state as the logic 1 state. 6. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. api (application programming interface) a series of software routines that comprise an interface between a computer application and lower level services and functions (for exampl e, user modules and libraries). apis serve as building blocks for programmers that create softwa re applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 73 of 80 bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perfo rm one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; fo r example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed frequen cy and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in whic h the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient te mperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data co mmunications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a comp uter to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allows the user to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. glossary (continued)
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 74 of 80 digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter pe rforms the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technol ogy that provides users with the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be pr otected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, vo ltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5 v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode an d 400 kbits/second in fast mode. ice the in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the ex ecution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exis t with its own priority and individual isr code block. each isr code block ends with the reti in struction, returning t he device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interr upt to the system when v dd falls lower than a selected threshold. glossary (continued)
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 75 of 80 m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the fl ash, sram, and register space. master device a device that controls the timing for da ta exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external in terface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a co ntroller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation bet ween the logical inputs and outputs of the psoc device and their physical counterparts in t he printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is lower than a pre-set level. this is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. glossary (continued)
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 76 of 80 rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device t hat sequentially shifts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, th e slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory . a memory device allowing users to store and retrieve data at a high rate of speed. the term static is used because, after a value has been loaded into an sram cell, it remains unchanged un til it is explicitly altered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output can adopt three states: 0, 1, and z (hig h-impedance). the function does not drive any value in the z state and, in many respects, may be c onsidered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modu les also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the registers in this bank are more likely to be modified during normal program execution and not just during initialization. register s in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of tim e. glossary (continued)
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 77 of 80 silicon errata for cy8c28243, cy8c28403, cy 8c28413, cy8c28433, cy8c28445, cy8c28452, cy8c28513, CY8C28533, cy8c28545, cy8c28623, cy8c28643, cy8c28645 this section describes the errata for cy8c28243, cy8c2840 3, cy8c28413, cy8c28433, cy8c 28445, cy8c28452, cy8c28513, CY8C28533, cy8c28545, cy8c28623, cy8c28643, cy8c28645 psoc devi ces. details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. please contact your local cypress sales representative if you have questions. part numbers affected qualification status engineering samples errata summary the following table defines the errata applicabili ty to cy8c28xxx devices. note each erratum in the table below is hyperlinked. click on the item entry to jump to its description. part number device characteristics cy8c28403 all variants cy8c28243 all variants cy8c28413 all variants cy8c28433 all variants cy8c28445 all variants cy8c28513 all variants CY8C28533 all variants cy8c28545 all variants cy8c28643 all variants cy8c28645 all variants cy8c28452 all variants cy8c28623 all variants items mpn silicon revision fix status cy8c28403 cy8c28413 cy8c28513 cy8c28433 CY8C28533 cy8c28243 cy8c28643 cy8c28445 cy8c28545 cy8c28645 es1 0 silicon fix planned before full device production starts. wrong data read from idac_crx and dacx_d registers cy8c28413 cy8c28513 cy8c28433 CY8C28533 cy8c28445 cy8c28545 cy8c28645 cy8c28452 es1 0 silicon fix planned before full device production starts.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 78 of 80 1. 10-bit sar adc does not meet dnl/inl specification. problem definition the 10-bit hardware sar adc does not meet datasheet accu racy specifications for dnl and inl under some conditions. parameters affected inlsar10: integral nonlinearity dnlsar10: differential nonlinearity trigger condition(s) the sar adc dnl has been measured greater than 2 lsb over temperatur e in all cases, as compared to the datasheet specification of 1.5 lsb. when using the vpwr (vdd) reference config uration, the sar adc dnl has been measured over temperature at 2 lsb for a supply voltage of 3.3v. with a supply voltage of 5.5v , the dnl has been measured greater than 3.5 lsb. scope of impact inaccurate converted data. workaround ? use an alternate adc implementation (delsi g, adcinc) available in cy8c28xxx devices. ? avoid cpu operations that change the addre ss and data buses while a-d conversion is r unning with internal vpwr (vdd) as vref. ? use un-buffered refhi as adc vref. this ma y have a negative effect on the analog blocks in the ana log array due to the noise introduced on refhi reference. fix status silicon fix is planned before full device production starts. 2. wrong data read from idac_crx and dacx_d registers. problem definition the cpu may read an incorrect value of bits 0, 3, 5, or 7 from the following registers: ? idac_cr0 ? idac_cr1 ? dac0_d ? dac1_d parameters affected fcpu1 and fcpu2 from the device data sheet. trigger condition(s) when cpu clock is set at its highest frequency setting (24 mhz nominal). scope of impact incorrect data read from affected registers. workaround temporarily slow down cpu clock frequency to 12 mhz nominal (or lower) when affected registers are read.
cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 document number: 001-48111 rev. *l page 79 of 80 document history page document title: cy8c28243, cy8c28403, cy8c28413, cy 8c28433, cy8c28445, cy8c28452, cy8c28513, CY8C28533, cy8c28545, cy8c28623, cy8c28643, cy8c2864 5 psoc? programmable system-on-chip? document number: 001-48111 revision ecn origin of change submission date description of change ** 2593460 btk/pyrs 10/20/08 new document (revision **). *a 2652217 btk/pyrs 02/02/09 extensive updates to content. added registers maps. updated getting started section updated development tools section added some sar10 adc specifications. added more analog system figures *b 2675937 btk 03/18/09 updated dc analog reference specifications tables minor content updates *c 2679015 hmi 03/26/2009 post to external web. *d 2750217 tdu 08/10/09 updates to electrical specifications section minor content updates *e 2768143 tdu 09/23/09 updated dc operational amplifier, dc analog reference, dc sar10adc, and dc por specifications; added fi gure 15 and figure 16; updated ac typee-operational and ac sar10adc specifications *f 2805324 alh 11/11/09 added contents page. updated electrical specifications . *g 2902396 njf 03/30/2010 updated cypress website links. added t baketemp and t baketime parameters in absolute maximum ratings . updated dc sar10 adc specifications . modified note 23. removed ac analog mux bus specificat ions, third party tools and build a psoc emulator into your board. updated packaging information and ordering code definitions . updated links in sales, solutions, and legal information . *h 3063584 njf 10/20/10 added psoc device characteristics table . added dc i2c specifications table. added f32k_u max limit. added tjit_imo specification, remo ved existing jitter specifications. updated analog reference tables. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changes were made to ac digital block specifications table and i2c timing diagram. they were updated for clearer understanding. updated figure 13 since the labelling for y-axis was incorrect. template and styles update. *i 3148779 njf 01/20/11 added footnote # 34 to thermal impedances section. table 7. 56-pin part pinout (ssop) (page 15) - pin#28 - pin name changed to"v ss ". table 5. 44-pin part pinout (tqfp) (page 13) - pin#17 - pin type changed to"power?. under dc sar10 adc specifications table, for parameter v vrefsar10 , max value changed from 4.95 v to v dd ? 0.3 v. updated table 59, ?solder reflow specifications,? on page 66 as per spec 25-00090. *j 3598237 lure/xzng 04/24/2012 changed the pwm description string from ?8- to 32-bit? to ?8- and 16-bit?. *k 3758002 gula 10/01/2012 updated packaging information (spec 001-45616 (changed revision from *b to *d), spec 51-85062 (changed revision from *d to *f)). *l 3993399 gvh 05/08/2013 updated reference documents (removed 001-17397 spec, 001-14503 spec related information). added silicon errata for cy8c28243, cy 8c28403, cy8c28413, cy8c28433, cy8c28445, cy8c28452, cy8c28 513, CY8C28533, cy8c28545, cy8c28623, cy8c28643, cy8c28645 .
document number: 001-48111 rev. *l revised may 8, 2013 page 80 of 80 psoc designer? and programmable system-on-chip? are trademarks and psoc? and capsense? are registered trademarks of cypress sem iconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c28243, cy8c28403, cy8c28413 cy8c28433, cy8c28445, cy8c28452 cy8c28513, CY8C28533, cy8c28545 cy8c28623, cy8c28643, cy8c28645 ? cypress semiconductor corporation, 2008-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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